CSRNG Simulation Results

Wednesday March 05 2025 15:08:10 UTC

GitHub Revision: `93c6c57959`

Branch: darjeeling-dv

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	csrng_smoke	5.000s	72.316us	1	1	100.00
V1	csr_hw_reset	csrng_csr_hw_reset	4.000s	21.840us	1	1	100.00
V1	csr_rw	csrng_csr_rw	5.000s	27.874us	1	1	100.00
V1	csr_bit_bash	csrng_csr_bit_bash	11.000s	304.143us	1	1	100.00
V1	csr_aliasing	csrng_csr_aliasing	6.000s	65.687us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	csrng_csr_mem_rw_with_rand_reset	45.650m		0	1	0.00
V1	regwen_csr_and_corresponding_lockable_csr	csrng_csr_rw	5.000s	27.874us	1	1	100.00
		csrng_csr_aliasing	6.000s	65.687us	1	1	100.00
V1		TOTAL			5	6	83.33
V2	interrupts	csrng_intr	7.000s	202.396us	1	1	100.00
V2	alerts	csrng_alert	16.000s	782.676us	1	1	100.00
V2	err	csrng_err	5.000s	35.396us	1	1	100.00
V2	cmds	csrng_cmds	3.150m	17.919ms	1	1	100.00
V2	life cycle	csrng_cmds	3.150m	17.919ms	1	1	100.00
V2	stress_all	csrng_stress_all	4.433m	16.691ms	1	1	100.00
V2	intr_test	csrng_intr_test	4.000s	18.535us	1	1	100.00
V2	alert_test	csrng_alert_test	5.000s	17.400us	1	1	100.00
V2	tl_d_oob_addr_access	csrng_tl_errors	6.000s	68.704us	1	1	100.00
V2	tl_d_illegal_access	csrng_tl_errors	6.000s	68.704us	1	1	100.00
V2	tl_d_outstanding_access	csrng_csr_hw_reset	4.000s	21.840us	1	1	100.00
		csrng_csr_rw	5.000s	27.874us	1	1	100.00
		csrng_csr_aliasing	6.000s	65.687us	1	1	100.00
		csrng_same_csr_outstanding	5.000s	38.942us	1	1	100.00
V2	tl_d_partial_access	csrng_csr_hw_reset	4.000s	21.840us	1	1	100.00
		csrng_csr_rw	5.000s	27.874us	1	1	100.00
		csrng_csr_aliasing	6.000s	65.687us	1	1	100.00
		csrng_same_csr_outstanding	5.000s	38.942us	1	1	100.00
V2		TOTAL			9	9	100.00
V2S	tl_intg_err	csrng_sec_cm	6.000s	83.145us	1	1	100.00
		csrng_tl_intg_err	6.000s	97.213us	1	1	100.00
V2S	sec_cm_config_regwen	csrng_regwen	5.000s	21.468us	1	1	100.00
		csrng_csr_rw	5.000s	27.874us	1	1	100.00
V2S	sec_cm_config_mubi	csrng_alert	16.000s	782.676us	1	1	100.00
V2S	sec_cm_intersig_mubi	csrng_stress_all	4.433m	16.691ms	1	1	100.00
V2S	sec_cm_main_sm_fsm_sparse	csrng_intr	7.000s	202.396us	1	1	100.00
		csrng_err	5.000s	35.396us	1	1	100.00
		csrng_sec_cm	6.000s	83.145us	1	1	100.00
V2S	sec_cm_update_fsm_sparse	csrng_intr	7.000s	202.396us	1	1	100.00
		csrng_err	5.000s	35.396us	1	1	100.00
		csrng_sec_cm	6.000s	83.145us	1	1	100.00
V2S	sec_cm_blk_enc_fsm_sparse	csrng_intr	7.000s	202.396us	1	1	100.00
		csrng_err	5.000s	35.396us	1	1	100.00
		csrng_sec_cm	6.000s	83.145us	1	1	100.00
V2S	sec_cm_outblk_fsm_sparse	csrng_intr	7.000s	202.396us	1	1	100.00
		csrng_err	5.000s	35.396us	1	1	100.00
		csrng_sec_cm	6.000s	83.145us	1	1	100.00
V2S	sec_cm_gen_cmd_ctr_redun	csrng_intr	7.000s	202.396us	1	1	100.00
		csrng_err	5.000s	35.396us	1	1	100.00
		csrng_sec_cm	6.000s	83.145us	1	1	100.00
V2S	sec_cm_drbg_upd_ctr_redun	csrng_intr	7.000s	202.396us	1	1	100.00
		csrng_err	5.000s	35.396us	1	1	100.00
		csrng_sec_cm	6.000s	83.145us	1	1	100.00
V2S	sec_cm_drbg_gen_ctr_redun	csrng_intr	7.000s	202.396us	1	1	100.00
		csrng_err	5.000s	35.396us	1	1	100.00
		csrng_sec_cm	6.000s	83.145us	1	1	100.00
V2S	sec_cm_ctrl_mubi	csrng_alert	16.000s	782.676us	1	1	100.00
V2S	sec_cm_main_sm_ctr_local_esc	csrng_intr	7.000s	202.396us	1	1	100.00
		csrng_err	5.000s	35.396us	1	1	100.00
V2S	sec_cm_constants_lc_gated	csrng_stress_all	4.433m	16.691ms	1	1	100.00
V2S	sec_cm_sw_genbits_bus_consistency	csrng_alert	16.000s	782.676us	1	1	100.00
V2S	sec_cm_tile_link_bus_integrity	csrng_tl_intg_err	6.000s	97.213us	1	1	100.00
V2S	sec_cm_aes_cipher_fsm_sparse	csrng_intr	7.000s	202.396us	1	1	100.00
		csrng_err	5.000s	35.396us	1	1	100.00
		csrng_sec_cm	6.000s	83.145us	1	1	100.00
V2S	sec_cm_aes_cipher_fsm_redun	csrng_intr	7.000s	202.396us	1	1	100.00
		csrng_err	5.000s	35.396us	1	1	100.00
V2S	sec_cm_aes_cipher_ctrl_sparse	csrng_intr	7.000s	202.396us	1	1	100.00
		csrng_err	5.000s	35.396us	1	1	100.00
V2S	sec_cm_aes_cipher_fsm_local_esc	csrng_intr	7.000s	202.396us	1	1	100.00
		csrng_err	5.000s	35.396us	1	1	100.00
V2S	sec_cm_aes_cipher_ctr_redun	csrng_intr	7.000s	202.396us	1	1	100.00
		csrng_err	5.000s	35.396us	1	1	100.00
		csrng_sec_cm	6.000s	83.145us	1	1	100.00
V2S	sec_cm_aes_cipher_data_reg_local_esc	csrng_intr	7.000s	202.396us	1	1	100.00
		csrng_err	5.000s	35.396us	1	1	100.00
V2S		TOTAL			3	3	100.00
V3	stress_all_with_rand_reset	csrng_stress_all_with_rand_reset	9.000s	182.144us	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			17	19	89.47

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:891) [csrng_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
- Test csrng_stress_all_with_rand_reset has 1 failures.
  - 0.csrng_stress_all_with_rand_reset.1
    Line 100, in log /nightly/runs/scratch/darjeeling-dv/csrng-sim-xcelium/0.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 182143980 ps: (cip_base_vseq.sv:891) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 182143980 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

Job returned non-zero exit code has 1 failures:

Test csrng_csr_mem_rw_with_rand_reset has 1 failures.

0.csrng_csr_mem_rw_with_rand_reset.1
Log /nightly/runs/scratch/darjeeling-dv/csrng-sim-xcelium/0.csrng_csr_mem_rw_with_rand_reset/latest/run.log

  1000 ps: (../src/lowrisc_dv_csrng_cov_0/csrng_cov_if.sv:554) [tb.dut.u_csrng_cov_if] Creating covergroup csrng_sts_cg
  1000 ps: (../src/lowrisc_dv_csrng_cov_0/csrng_cov_if.sv:555) [tb.dut.u_csrng_cov_if] Creating covergroup csrng_err_code_cg
  1000 ps: (../src/lowrisc_dv_csrng_cov_0/csrng_cov_if.sv:556) [tb.dut.u_csrng_cov_if] Creating covergroup csrng_err_code_test_cg
  1000 ps: (../src/lowrisc_dv_csrng_cov_0/csrng_cov_if.sv:557) [tb.dut.u_csrng_cov_if] Creating covergroup csrng_recov_alert_sts_cg
  1000 ps: (../src/lowrisc_dv_csrng_cov_0/csrng_cov_if.sv:558) [tb.dut.u_csrng_cov_if] Creating covergroup csrng_otp_en_sw_app_read_cg
  1000 ps: (../src/lowrisc_dv_csrng_cov_0/csrng_cov_if.sv:559) [tb.dut.u_csrng_cov_if] Creating covergroup csrng_genbits_cg
  1000 ps: (../src/lowrisc_dv_csrng_cov_0/csrng_cov_if.sv:560) [tb.dut.u_csrng_cov_if] Creating covergroup csrng_state_db_cg
  1000 ps: (../src/lowrisc_dv_csrng_cov_0/csrng_cov_if.sv:561) [tb.dut.u_csrng_cov_if] Creating covergroup csrng_es_sample_cg
  xmsim: *W,COVDCG: (File: /nightly/runs/scratch/darjeeling-dv/csrng-sim-xcelium/cover_reg_top/src/lowrisc_dv_dv_base_reg_0/dv_base_mubi_cov.sv, Line: 21):(Time: 1281202 PS + 2) Covergroup instance (worklib.dv_base_reg_pkg::mubi_cov#(4,6,9)::mubi_cg@4539), is garbage collected. Its instance coverage will not be reported separately and instead accumulated into corresponding type-coverage (dv_base_reg_pkg.mubi_cov#(4, 6, 9)::mubi_cg).
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:191: simulate] Killed