DMA Simulation Results

Wednesday March 05 2025 15:08:10 UTC

GitHub Revision: 93c6c57959

Branch: darjeeling-dv

Testplan

Simulator: XCELIUM

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 dma_memory_smoke dma_memory_smoke 6.000s 1.230ms 1 1 100.00
V1 dma_handshake_smoke dma_handshake_smoke 6.000s 1.284ms 1 1 100.00
V1 dma_generic_smoke dma_generic_smoke 7.000s 1.573ms 1 1 100.00
V1 csr_hw_reset dma_csr_hw_reset 4.000s 84.741us 1 1 100.00
V1 csr_rw dma_csr_rw 4.000s 91.341us 1 1 100.00
V1 csr_bit_bash dma_csr_bit_bash 9.000s 3.735ms 1 1 100.00
V1 csr_aliasing dma_csr_aliasing 7.000s 1.373ms 1 1 100.00
V1 csr_mem_rw_with_rand_reset dma_csr_mem_rw_with_rand_reset 0 1 0.00
V1 regwen_csr_and_corresponding_lockable_csr dma_csr_rw 4.000s 91.341us 1 1 100.00
dma_csr_aliasing 7.000s 1.373ms 1 1 100.00
V1 TOTAL 7 8 87.50
V2 dma_memory_region_lock dma_memory_region_lock 38.000s 15.846ms 1 1 100.00
V2 dma_handshake_stress dma_handshake_stress 6.033m 207.697ms 1 1 100.00
V2 dma_memory_stress dma_memory_stress 24.333m 902.889ms 1 1 100.00
V2 dma_generic_stress dma_generic_stress 4.683m 150.731ms 1 1 100.00
V2 dma_handshake_mem_buffer_overflow dma_handshake_stress 6.033m 207.697ms 1 1 100.00
V2 dma_abort dma_abort 12.000s 4.510ms 1 1 100.00
V2 dma_stress_all dma_stress_all 2.567m 67.501ms 1 1 100.00
V2 intr_test dma_intr_test 4.000s 50.791us 1 1 100.00
V2 tl_d_oob_addr_access dma_tl_errors 5.000s 315.941us 1 1 100.00
V2 tl_d_illegal_access dma_tl_errors 5.000s 315.941us 1 1 100.00
V2 tl_d_outstanding_access dma_csr_hw_reset 4.000s 84.741us 1 1 100.00
dma_csr_rw 4.000s 91.341us 1 1 100.00
dma_csr_aliasing 7.000s 1.373ms 1 1 100.00
dma_same_csr_outstanding 5.000s 306.741us 1 1 100.00
V2 tl_d_partial_access dma_csr_hw_reset 4.000s 84.741us 1 1 100.00
dma_csr_rw 4.000s 91.341us 1 1 100.00
dma_csr_aliasing 7.000s 1.373ms 1 1 100.00
dma_same_csr_outstanding 5.000s 306.741us 1 1 100.00
V2 TOTAL 9 9 100.00
V2S dma_illegal_addr_range dma_mem_enabled 31.000s 1.776ms 1 1 100.00
dma_generic_stress 4.683m 150.731ms 1 1 100.00
dma_handshake_stress 6.033m 207.697ms 1 1 100.00
V2S tl_intg_err dma_tl_intg_err 5.000s 547.241us 1 1 100.00
V2S TOTAL 2 2 100.00
Unmapped tests dma_short_transfer 2.100m 76.319ms 1 1 100.00
dma_longer_transfer 11.000s 2.654ms 1 1 100.00
TOTAL 20 21 95.24

Failure Buckets