KEYMGR_DPE Simulation Results

Wednesday March 05 2025 15:08:10 UTC

GitHub Revision: 93c6c57959

Branch: darjeeling-dv

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	keymgr_dpe_smoke	10.970s	1.652ms	1	1	100.00
V1	csr_hw_reset	keymgr_dpe_csr_hw_reset	1.690s	57.536us	1	1	100.00
V1	csr_rw	keymgr_dpe_csr_rw	1.680s	55.494us	1	1	100.00
V1	csr_bit_bash	keymgr_dpe_csr_bit_bash	7.270s	1.202ms	1	1	100.00
V1	csr_aliasing	keymgr_dpe_csr_aliasing	4.210s	467.039us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	keymgr_dpe_csr_mem_rw_with_rand_reset	1.910s	87.827us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	keymgr_dpe_csr_rw	1.680s	55.494us	1	1	100.00
		keymgr_dpe_csr_aliasing	4.210s	467.039us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	intr_test	keymgr_dpe_intr_test	1.460s	30.285us	1	1	100.00
V2	alert_test	keymgr_dpe_alert_test	1.520s	38.869us	1	1	100.00
V2	tl_d_oob_addr_access	keymgr_dpe_tl_errors	2.790s	249.162us	1	1	100.00
V2	tl_d_illegal_access	keymgr_dpe_tl_errors	2.790s	249.162us	1	1	100.00
V2	tl_d_outstanding_access	keymgr_dpe_csr_hw_reset	1.690s	57.536us	1	1	100.00
		keymgr_dpe_csr_rw	1.680s	55.494us	1	1	100.00
		keymgr_dpe_csr_aliasing	4.210s	467.039us	1	1	100.00
		keymgr_dpe_same_csr_outstanding	2.390s	165.328us	1	1	100.00
V2	tl_d_partial_access	keymgr_dpe_csr_hw_reset	1.690s	57.536us	1	1	100.00
		keymgr_dpe_csr_rw	1.680s	55.494us	1	1	100.00
		keymgr_dpe_csr_aliasing	4.210s	467.039us	1	1	100.00
		keymgr_dpe_same_csr_outstanding	2.390s	165.328us	1	1	100.00
V2		TOTAL			4	4	100.00
V2S	tl_intg_err	keymgr_dpe_sec_cm	6.980s	1.094ms	1	1	100.00
		keymgr_dpe_tl_intg_err	3.780s	362.621us	1	1	100.00
V2S	shadow_reg_update_error	keymgr_dpe_shadow_reg_errors	2.480s	208.578us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	keymgr_dpe_shadow_reg_errors	2.480s	208.578us	1	1	100.00
V2S	shadow_reg_storage_error	keymgr_dpe_shadow_reg_errors	2.480s	208.578us	1	1	100.00
V2S	shadowed_reset_glitch	keymgr_dpe_shadow_reg_errors	2.480s	208.578us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	keymgr_dpe_shadow_reg_errors_with_csr_rw	4.150s	441.330us	1	1	100.00
V2S	prim_count_check	keymgr_dpe_sec_cm	6.980s	1.094ms	1	1	100.00
V2S	prim_fsm_check	keymgr_dpe_sec_cm	6.980s	1.094ms	1	1	100.00
V2S		TOTAL			4	4	100.00
		TOTAL			14	14	100.00