SPI_HOST Simulation Results

Wednesday March 05 2025 15:08:10 UTC

GitHub Revision: 93c6c57959

Branch: darjeeling-dv

Testplan

Simulator: XCELIUM

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke spi_host_smoke 58.000s 18.843ms 1 1 100.00
V1 csr_hw_reset spi_host_csr_hw_reset 3.000s 51.841us 1 1 100.00
V1 csr_rw spi_host_csr_rw 3.000s 65.691us 1 1 100.00
V1 csr_bit_bash spi_host_csr_bit_bash 4.000s 414.641us 1 1 100.00
V1 csr_aliasing spi_host_csr_aliasing 3.000s 86.391us 1 1 100.00
V1 csr_mem_rw_with_rand_reset spi_host_csr_mem_rw_with_rand_reset 0 1 0.00
V1 regwen_csr_and_corresponding_lockable_csr spi_host_csr_rw 3.000s 65.691us 1 1 100.00
spi_host_csr_aliasing 3.000s 86.391us 1 1 100.00
V1 mem_walk spi_host_mem_walk 3.000s 53.641us 1 1 100.00
V1 mem_partial_access spi_host_mem_partial_access 3.000s 69.091us 1 1 100.00
V1 TOTAL 7 8 87.50
V2 performance spi_host_performance 14.000s 111.291us 1 1 100.00
V2 error_event_intr spi_host_overflow_underflow 6.000s 613.091us 1 1 100.00
spi_host_error_cmd 3.000s 51.191us 1 1 100.00
spi_host_event 10.000s 3.150ms 1 1 100.00
V2 clock_rate spi_host_speed 15.000s 417.691us 1 1 100.00
V2 speed spi_host_speed 15.000s 417.691us 1 1 100.00
V2 chip_select_timing spi_host_speed 15.000s 417.691us 1 1 100.00
V2 sw_reset spi_host_sw_reset 8.000s 207.741us 1 1 100.00
V2 passthrough_mode spi_host_passthrough_mode 4.000s 1.571ms 1 1 100.00
V2 cpol_cpha spi_host_speed 15.000s 417.691us 1 1 100.00
V2 full_cycle spi_host_speed 15.000s 417.691us 1 1 100.00
V2 duplex spi_host_smoke 58.000s 18.843ms 1 1 100.00
V2 tx_rx_only spi_host_smoke 58.000s 18.843ms 1 1 100.00
V2 stress_all spi_host_stress_all 6.000s 734.041us 1 1 100.00
V2 spien spi_host_spien 4.000s 1.325ms 1 1 100.00
V2 stall spi_host_status_stall 34.000s 9.179ms 1 1 100.00
V2 Idlecsbactive spi_host_idlecsbactive 4.000s 241.041us 1 1 100.00
V2 data_fifo_status spi_host_overflow_underflow 6.000s 613.091us 1 1 100.00
V2 alert_test spi_host_alert_test 3.000s 56.441us 1 1 100.00
V2 intr_test spi_host_intr_test 3.000s 52.391us 1 1 100.00
V2 tl_d_oob_addr_access spi_host_tl_errors 4.000s 304.391us 1 1 100.00
V2 tl_d_illegal_access spi_host_tl_errors 4.000s 304.391us 1 1 100.00
V2 tl_d_outstanding_access spi_host_csr_hw_reset 3.000s 51.841us 1 1 100.00
spi_host_csr_rw 3.000s 65.691us 1 1 100.00
spi_host_csr_aliasing 3.000s 86.391us 1 1 100.00
spi_host_same_csr_outstanding 3.000s 65.641us 1 1 100.00
V2 tl_d_partial_access spi_host_csr_hw_reset 3.000s 51.841us 1 1 100.00
spi_host_csr_rw 3.000s 65.691us 1 1 100.00
spi_host_csr_aliasing 3.000s 86.391us 1 1 100.00
spi_host_same_csr_outstanding 3.000s 65.641us 1 1 100.00
V2 TOTAL 15 15 100.00
V2S tl_intg_err spi_host_tl_intg_err 4.000s 218.441us 1 1 100.00
spi_host_sec_cm 3.000s 205.241us 1 1 100.00
V2S sec_cm_bus_integrity spi_host_tl_intg_err 4.000s 218.441us 1 1 100.00
V2S TOTAL 2 2 100.00
Unmapped tests spi_host_upper_range_clkdiv 9.333m 45.345ms 1 1 100.00
TOTAL 25 26 96.15

Failure Buckets