371772adfd| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | mbx_smoke | mbx_smoke | 43.000s | 6.549ms | 1 | 1 | 100.00 |
| V1 | csr_hw_reset | mbx_csr_hw_reset | 6.000s | 24.738us | 1 | 1 | 100.00 |
| V1 | csr_rw | mbx_csr_rw | 6.000s | 20.350us | 1 | 1 | 100.00 |
| V1 | csr_bit_bash | mbx_csr_bit_bash | 4.000s | 110.166us | 1 | 1 | 100.00 |
| V1 | csr_aliasing | mbx_csr_aliasing | 4.000s | 21.738us | 1 | 1 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | mbx_csr_mem_rw_with_rand_reset | 4.000s | 2.044us | 0 | 1 | 0.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | mbx_csr_rw | 6.000s | 20.350us | 1 | 1 | 100.00 |
| mbx_csr_aliasing | 4.000s | 21.738us | 1 | 1 | 100.00 | ||
| V1 | TOTAL | 5 | 6 | 83.33 | |||
| V2 | mbx_stress | mbx_stress | 53.000s | 10.248ms | 1 | 1 | 100.00 |
| mbx_stress_zero_delays | 41.000s | 1.451ms | 1 | 1 | 100.00 | ||
| V2 | mbx_imbx_oob | mbx_imbx_oob | 28.000s | 5.002ms | 1 | 1 | 100.00 |
| V2 | alert_test | mbx_alert_test | 10.000s | 20.881us | 1 | 1 | 100.00 |
| V2 | tl_d_oob_addr_access | mbx_tl_errors | 8.000s | 2.044us | 0 | 1 | 0.00 |
| V2 | tl_d_illegal_access | mbx_tl_errors | 8.000s | 2.044us | 0 | 1 | 0.00 |
| V2 | tl_d_outstanding_access | mbx_csr_hw_reset | 6.000s | 24.738us | 1 | 1 | 100.00 |
| mbx_csr_rw | 6.000s | 20.350us | 1 | 1 | 100.00 | ||
| mbx_csr_aliasing | 4.000s | 21.738us | 1 | 1 | 100.00 | ||
| mbx_same_csr_outstanding | 4.000s | 23.656us | 1 | 1 | 100.00 | ||
| V2 | tl_d_partial_access | mbx_csr_hw_reset | 6.000s | 24.738us | 1 | 1 | 100.00 |
| mbx_csr_rw | 6.000s | 20.350us | 1 | 1 | 100.00 | ||
| mbx_csr_aliasing | 4.000s | 21.738us | 1 | 1 | 100.00 | ||
| mbx_same_csr_outstanding | 4.000s | 23.656us | 1 | 1 | 100.00 | ||
| V2 | TOTAL | 5 | 6 | 83.33 | |||
| V2S | tl_intg_err | mbx_sec_cm | 10.000s | 17.595us | 1 | 1 | 100.00 |
| mbx_tl_intg_err | 6.000s | 11.146us | 0 | 1 | 0.00 | ||
| V2S | TOTAL | 1 | 2 | 50.00 | |||
| TOTAL | 11 | 14 | 78.57 |
UVM_ERROR (tl_host_seq.sv:55) sequencer [tl_seq] fail to find matching req for rsp[*]: a_addr = * a_data = * a_mask = * a_size = * a_param = * a_source = * a_opcode = Get a_user = * d_data = * d_size = * d_param = * d_source = * d_opcode = AccessAckData d_error = * d_user = * d_sink = * req_abort_after_a_valid_len = * rsp_abort_after_d_valid_len = * req_completed = * rsp_completed = * has 2 failures:
Test mbx_tl_intg_err has 1 failures.
0.mbx_tl_intg_err.1
Line 95, in log /nightly/runs/scratch/dj-sw-nightly/mbx-sim-xcelium/0.mbx_tl_intg_err/latest/run.log
UVM_ERROR @ 11146286 ps: (tl_host_seq.sv:55) uvm_test_top.env.m_tl_agent_mbx_mem_reg_block.sequencer [uvm_test_top.env.virtual_sequencer._item.tl_seq] fail to find matching req for rsp[0]: a_addr = 0xdaa2ecb6 a_data = 0x2b4e45c8 a_mask = 0x8 a_size = 0x1 a_param = 0x0 a_source = 0xed a_opcode = Get a_user = 0x24d2b d_data = 0xb8345aed d_size = 0x0 d_param = 0x0 d_source = 0x9 d_opcode = AccessAckData d_error = 0 d_user = 1110110010110 d_sink = 0 req_abort_after_a_valid_len = 0 rsp_abort_after_d_valid_len = 0 req_completed = 0 rsp_completed = 1
UVM_INFO @ 11146286 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test mbx_csr_mem_rw_with_rand_reset has 1 failures.
0.mbx_csr_mem_rw_with_rand_reset.1
Line 83, in log /nightly/runs/scratch/dj-sw-nightly/mbx-sim-xcelium/0.mbx_csr_mem_rw_with_rand_reset/latest/run.log
UVM_ERROR @ 2044318 ps: (tl_host_seq.sv:55) uvm_test_top.env.m_tl_agent_mbx_mem_reg_block.sequencer [uvm_test_top.env.virtual_sequencer._item.tl_seq] fail to find matching req for rsp[0]: a_addr = 0x15eb9c3d a_data = 0xfed8ba58 a_mask = 0x8 a_size = 0x2 a_param = 0x0 a_source = 0xed a_opcode = Get a_user = 0x2712b d_data = 0x1edbaf5c d_size = 0x1 d_param = 0x0 d_source = 0xe4 d_opcode = AccessAckData d_error = 0 d_user = 1011111001 d_sink = 0 req_abort_after_a_valid_len = 1 rsp_abort_after_d_valid_len = 0 req_completed = 0 rsp_completed = 1
UVM_INFO @ 2044318 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (tl_host_seq.sv:55) sequencer [tl_seq] fail to find matching req for rsp[*]: a_addr = * a_data = * a_mask = * a_size = * a_param = * a_source = * a_opcode = Get a_user = * d_data = * d_size = * d_param = * d_source = * d_opcode = AccessAck d_error = * d_user = * d_sink = * req_abort_after_a_valid_len = * rsp_abort_after_d_valid_len = * req_completed = * rsp_completed = * has 1 failures:
0.mbx_tl_errors.1
Line 82, in log /nightly/runs/scratch/dj-sw-nightly/mbx-sim-xcelium/0.mbx_tl_errors/latest/run.log
UVM_ERROR @ 2044318 ps: (tl_host_seq.sv:55) uvm_test_top.env.m_tl_agent_mbx_mem_reg_block.sequencer [uvm_test_top.env.virtual_sequencer._item.tl_seq] fail to find matching req for rsp[0]: a_addr = 0x2da32284 a_data = 0xef8ca863 a_mask = 0xf a_size = 0x2 a_param = 0x0 a_source = 0xed a_opcode = Get a_user = 0x109c1 d_data = 0xafb0a1d d_size = 0x1 d_param = 0x0 d_source = 0x69 d_opcode = AccessAck d_error = 0 d_user = 111000100011 d_sink = 0 req_abort_after_a_valid_len = 0 rsp_abort_after_d_valid_len = 0 req_completed = 0 rsp_completed = 1
UVM_INFO @ 2044318 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---