CHIP Simulation Results

Thursday March 13 2025 17:34:42 UTC

GitHub Revision: `9770f6b02e`

Branch: dj-sw-nightly

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	chip_sw_uart_tx_rx	chip_sw_uart_tx_rx	10.036s		0	1	0.00
V1	chip_sw_uart_rx_overflow	chip_sw_uart_tx_rx	10.036s		0	1	0.00
V1	chip_sw_uart_rand_baudrate	chip_sw_uart_rand_baudrate	10.054s		0	1	0.00
V1	chip_sw_uart_tx_rx_alt_clk_freq	chip_sw_uart_tx_rx_alt_clk_freq	10.051s		0	1	0.00
		chip_sw_uart_tx_rx_alt_clk_freq_low_speed	10.051s		0	1	0.00
V1	chip_sw_gpio_out	chip_sw_gpio	2.170m		0	1	0.00
V1	chip_sw_gpio_in	chip_sw_gpio	2.170m		0	1	0.00
V1	chip_sw_gpio_irq	chip_sw_gpio	2.170m		0	1	0.00
V1	chip_sw_example_tests	chip_sw_example_rom	14.017s		0	1	0.00
		chip_sw_example_manufacturer	10.014s		0	1	0.00
		chip_sw_example_concurrency	11.016s		0	1	0.00
		chip_sw_uart_smoketest_signed	13.081s		0	1	0.00
V1	csr_hw_reset	chip_csr_hw_reset	2.362m	3.702ms	0	1	0.00
V1	csr_rw	chip_csr_rw	2.425m	3.702ms	0	1	0.00
V1	csr_bit_bash	chip_csr_bit_bash	4.170m	5.185ms	1	1	100.00
V1	csr_aliasing	chip_csr_aliasing	2.336m	3.702ms	0	1	0.00
V1	csr_mem_rw_with_rand_reset	chip_csr_mem_rw_with_rand_reset	2.293m	3.702ms	0	1	0.00
V1	regwen_csr_and_corresponding_lockable_csr	chip_csr_aliasing	2.336m	3.702ms	0	1	0.00
		chip_csr_rw	2.425m	3.702ms	0	1	0.00
V1	xbar_smoke	xbar_smoke	14.370s	49.909us	1	1	100.00
V1		TOTAL			2	15	13.33
V2	chip_sw_spi_device_flash_mode	chip_sw_uart_tx_rx_bootstrap	10.053s		0	1	0.00
V2	chip_sw_spi_device_pass_through	chip_sw_spi_device_pass_through	6.198m	7.904ms	1	1	100.00
V2	chip_sw_spi_device_pass_through_collision	chip_sw_spi_device_pass_through_collision	3.857m	4.504ms	0	1	0.00
V2	chip_sw_spi_device_tpm	chip_sw_spi_device_tpm	10.046s		0	1	0.00
V2	chip_sw_spi_host_tx_rx	chip_sw_spi_host_tx_rx	10.044s		0	1	0.00
V2	chip_sw_i2c_host_tx_rx	chip_sw_i2c_host_tx_rx	10.046s		0	1	0.00
V2	chip_sw_i2c_device_tx_rx	chip_sw_i2c_device_tx_rx	10.044s		0	1	0.00
V2	chip_pin_mux	chip_padctrl_attributes	3.220s		0	1	0.00
V2	chip_padctrl_attributes	chip_padctrl_attributes	3.220s		0	1	0.00
V2	chip_sw_sleep_pin_wake	chip_sw_sleep_pin_wake	10.037s		0	1	0.00
V2	chip_sw_sleep_pin_retention	chip_sw_sleep_pin_retention	10.038s		0	1	0.00
V2	chip_sw_data_integrity	chip_sw_data_integrity_escalation	10.040s		0	1	0.00
V2	chip_sw_instruction_integrity	chip_sw_data_integrity_escalation	10.040s		0	1	0.00
V2	chip_jtag_csr_rw	chip_jtag_csr_rw	2.379m	3.683ms	0	1	0.00
V2	chip_jtag_mem_access	chip_jtag_mem_access	2.368m	3.683ms	0	1	0.00
V2	chip_rv_dm_ndm_reset_req	chip_rv_dm_ndm_reset_req	11.030s		0	1	0.00
V2	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	11.030s		0	1	0.00
V2	chip_rv_dm_access_after_wakeup	chip_sw_rv_dm_access_after_wakeup	10.060s		0	1	0.00
V2	chip_rv_dm_lc_disabled	chip_rv_dm_lc_disabled	10.084m	17.314ms	1	1	100.00
V2	chip_sw_timer	chip_sw_rv_timer_irq	4.253m	6.170ms	1	1	100.00
V2	chip_sw_aon_timer_wakeup_irq	chip_sw_aon_timer_irq	10.024s		0	1	0.00
V2	chip_sw_aon_timer_wdog_bark_irq	chip_sw_aon_timer_irq	10.024s		0	1	0.00
V2	chip_sw_aon_timer_wdog_lc_escalate	chip_sw_aon_timer_wdog_lc_escalate	10.040s		0	1	0.00
V2	chip_sw_aon_timer_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	10.039s		0	1	0.00
V2	chip_sw_aon_timer_sleep_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	10.039s		0	1	0.00
V2	chip_sw_aon_timer_sleep_wdog_sleep_pause	chip_sw_aon_timer_sleep_wdog_sleep_pause	10.031s		0	1	0.00
V2	chip_sw_plic_all_irqs	chip_plic_all_irqs	10.026s		0	1	0.00
V2	chip_sw_plic_sw_irq	chip_sw_plic_sw_irq	2.951m	4.132ms	1	1	100.00
V2	chip_sw_clkmgr_idle_trans	chip_sw_otbn_randomness	4.740m	4.839ms	1	1	100.00
		chip_sw_aes_idle	3.144m	4.137ms	1	1	100.00
		chip_sw_hmac_enc_idle	10.043s		0	1	0.00
		chip_sw_kmac_idle	3.049m	4.099ms	1	1	100.00
V2	chip_sw_clkmgr_off_trans	chip_sw_clkmgr_off_aes_trans	11.026s		0	1	0.00
		chip_sw_clkmgr_off_hmac_trans	11.031s		0	1	0.00
		chip_sw_clkmgr_off_kmac_trans	11.028s		0	1	0.00
		chip_sw_clkmgr_off_otbn_trans	11.049s		0	1	0.00
V2	chip_sw_clkmgr_div	chip_sw_clkmgr_external_clk_src_for_lc	10.043s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	11.062s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	10.049s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	10.056s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	10.054s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	11.052s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	11.050s		0	1	0.00
V2	chip_sw_clkmgr_external_clk_src_for_lc	chip_sw_clkmgr_external_clk_src_for_lc	10.043s		0	1	0.00
V2	chip_sw_clkmgr_external_clk_src_for_sw	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	11.062s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	10.049s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	10.056s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	10.054s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	11.052s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	11.050s		0	1	0.00
V2	chip_sw_clkmgr_jitter	chip_sw_otbn_ecdsa_op_irq_jitter_en	11.033s		0	1	0.00
		chip_sw_aes_enc_jitter_en	41.910s	10.200us	0	1	0.00
		chip_sw_edn_entropy_reqs_jitter	11.052s		0	1	0.00
		chip_sw_hmac_enc_jitter_en	11.050s		0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	44.620s	10.200us	0	1	0.00
		chip_sw_kmac_mode_kmac_jitter_en	43.530s	10.200us	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	10.039s		0	1	0.00
		chip_sw_clkmgr_jitter	2.974m	4.046ms	1	1	100.00
V2	chip_sw_clkmgr_extended_range	chip_sw_clkmgr_jitter_reduced_freq	2.972m	4.046ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq	12.017s		0	1	0.00
		chip_sw_aes_enc_jitter_en_reduced_freq	42.900s	10.200us	0	1	0.00
		chip_sw_hmac_enc_jitter_en_reduced_freq	13.020s		0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en_reduced_freq	42.480s	10.200us	0	1	0.00
		chip_sw_kmac_mode_kmac_jitter_en_reduced_freq	42.370s	10.200us	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq	11.019s		0	1	0.00
		chip_sw_csrng_edn_concurrency_reduced_freq	11.016s		0	1	0.00
V2	chip_sw_clkmgr_deep_sleep_frequency	chip_sw_ast_clk_outputs	11.029s		0	1	0.00
V2	chip_sw_clkmgr_sleep_frequency	chip_sw_clkmgr_sleep_frequency	11.044s		0	1	0.00
V2	chip_sw_clkmgr_reset_frequency	chip_sw_clkmgr_reset_frequency	11.053s		0	1	0.00
V2	chip_sw_clkmgr_escalation_reset	chip_sw_all_escalation_resets	10.021s		0	1	0.00
V2	chip_sw_pwrmgr_external_full_reset	chip_sw_pwrmgr_full_aon_reset	11.032s		0	1	0.00
V2	chip_sw_pwrmgr_sleep_all_reset_reqs	chip_sw_aon_timer_wdog_bite_reset	10.039s		0	1	0.00
V2	chip_sw_pwrmgr_wdog_reset	chip_sw_pwrmgr_wdog_reset	10.039s		0	1	0.00
V2	chip_sw_pwrmgr_aon_power_glitch_reset	chip_sw_pwrmgr_full_aon_reset	11.032s		0	1	0.00
V2	chip_sw_pwrmgr_main_power_glitch_reset	chip_sw_pwrmgr_main_power_glitch_reset	11.031s		0	1	0.00
V2	chip_sw_pwrmgr_random_sleep_power_glitch_reset	chip_sw_pwrmgr_random_sleep_power_glitch_reset	10.030s		0	1	0.00
V2	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	10.030s		0	1	0.00
V2	chip_sw_pwrmgr_sleep_power_glitch_reset	chip_sw_pwrmgr_sleep_power_glitch_reset	11.028s		0	1	0.00
V2	chip_sw_pwrmgr_sleep_disabled	chip_sw_pwrmgr_sleep_disabled	11.028s		0	1	0.00
V2	chip_sw_pwrmgr_escalation_reset	chip_sw_all_escalation_resets	10.021s		0	1	0.00
V2	chip_sw_rstmgr_sys_reset_info	chip_rv_dm_ndm_reset_req	11.030s		0	1	0.00
V2	chip_sw_rstmgr_cpu_info	chip_sw_rstmgr_cpu_info	12.908m	20.027ms	0	1	0.00
V2	chip_sw_rstmgr_sw_req_reset	chip_sw_rstmgr_sw_req	8.062m	12.027ms	0	1	0.00
V2	chip_sw_rstmgr_alert_info	chip_sw_rstmgr_alert_info	10.027s		0	1	0.00
V2	chip_sw_rstmgr_sw_rst	chip_sw_rstmgr_sw_rst	11.034s		0	1	0.00
V2	chip_sw_rstmgr_escalation_reset	chip_sw_all_escalation_resets	10.021s		0	1	0.00
V2	chip_sw_alert_handler_alerts	chip_sw_alert_test	10.011s		0	1	0.00
V2	chip_sw_alert_handler_escalations	chip_sw_alert_handler_escalation	10.019s		0	1	0.00
V2	chip_sw_all_escalation_resets	chip_sw_all_escalation_resets	10.021s		0	1	0.00
V2	chip_sw_alert_handler_irqs	chip_plic_all_irqs	10.026s		0	1	0.00
V2	chip_sw_alert_handler_entropy	chip_sw_alert_handler_entropy	11.024s		0	1	0.00
V2	chip_sw_alert_handler_crashdump	chip_sw_rstmgr_alert_info	10.027s		0	1	0.00
V2	chip_sw_alert_handler_ping_timeout	chip_sw_alert_handler_ping_timeout	10.021s		0	1	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_alerts	chip_sw_alert_handler_lpg_sleep_mode_alerts	10.034s		0	1	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_pings	chip_sw_alert_handler_lpg_sleep_mode_pings	10.033s		0	1	0.00
V2	chip_sw_alert_handler_lpg_clock_off	chip_sw_alert_handler_lpg_clkoff	10.028s		0	1	0.00
V2	chip_sw_alert_handler_lpg_reset_toggle	chip_sw_alert_handler_lpg_reset_toggle	10.025s		0	1	0.00
V2	chip_sw_alert_handler_reverse_ping_in_deep_sleep	chip_sw_alert_handler_reverse_ping_in_deep_sleep	10.024s		0	1	0.00
V2	chip_sw_lc_ctrl_alert_handler_escalation	chip_sw_alert_handler_escalation	10.019s		0	1	0.00
V2	chip_sw_lc_ctrl_jtag_access	chip_sw_lc_ctrl_transition	11.051s		0	1	0.00
V2	chip_sw_lc_ctrl_otp_hw_cfg	chip_sw_lc_ctrl_otp_hw_cfg	2.069m		0	1	0.00
V2	chip_sw_lc_ctrl_init	chip_sw_lc_ctrl_transition	11.051s		0	1	0.00
V2	chip_sw_lc_ctrl_transitions	chip_sw_lc_ctrl_transition	11.051s		0	1	0.00
V2	chip_sw_lc_ctrl_kmac_req	chip_sw_lc_ctrl_transition	11.051s		0	1	0.00
V2	chip_sw_lc_ctrl_key_div	chip_sw_keymgr_dpe_key_derivation_prod	5.234m	6.939ms	0	1	0.00
V2	chip_sw_lc_ctrl_broadcast	chip_sw_otp_ctrl_lc_signals_test_unlocked0	1.969m		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_dev	1.651m		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_prod	1.485m		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_rma	1.401m		0	1	0.00
		chip_sw_lc_ctrl_transition	11.051s		0	1	0.00
		chip_sw_keymgr_dpe_key_derivation	5.491m	6.939ms	0	1	0.00
		chip_sw_rom_ctrl_integrity_check	7.633m	11.740ms	1	1	100.00
		chip_sw_sram_ctrl_execution_main	10.032s		0	1	0.00
		chip_prim_tl_access	8.847m	13.660ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_lc	10.043s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	11.062s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	10.049s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	10.056s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	10.054s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	11.052s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	11.050s		0	1	0.00
		chip_rv_dm_lc_disabled	10.084m	17.314ms	1	1	100.00
V2	chip_sw_aes_enc	chip_sw_aes_enc	3.398m	4.349ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	41.910s	10.200us	0	1	0.00
V2	chip_sw_aes_entropy	chip_sw_aes_entropy	9.538m	15.027ms	0	1	0.00
V2	chip_sw_aes_idle	chip_sw_aes_idle	3.144m	4.137ms	1	1	100.00
V2	chip_sw_hmac_enc	chip_sw_hmac_enc	11.050s		0	1	0.00
		chip_sw_hmac_enc_jitter_en	11.050s		0	1	0.00
V2	chip_sw_hmac_idle	chip_sw_hmac_enc_idle	10.043s		0	1	0.00
V2	chip_sw_kmac_enc	chip_sw_kmac_mode_cshake	7.887m	12.027ms	0	1	0.00
		chip_sw_kmac_mode_kmac	7.729m	12.027ms	0	1	0.00
		chip_sw_kmac_mode_kmac_jitter_en	43.530s	10.200us	0	1	0.00
V2	chip_sw_kmac_app_keymgr	chip_sw_keymgr_dpe_key_derivation	5.491m	6.939ms	0	1	0.00
V2	chip_sw_kmac_app_lc	chip_sw_lc_ctrl_transition	11.051s		0	1	0.00
V2	chip_sw_kmac_app_rom	chip_sw_kmac_app_rom	36.420s	10.200us	0	1	0.00
V2	chip_sw_kmac_entropy	chip_sw_kmac_entropy	2.052m		0	1	0.00
V2	chip_sw_kmac_idle	chip_sw_kmac_idle	3.049m	4.099ms	1	1	100.00
V2	chip_sw_entropy_src_csrng	chip_sw_entropy_src_csrng	11.010s		0	1	0.00
V2	chip_sw_csrng_edn_cmd	chip_sw_entropy_src_csrng	11.010s		0	1	0.00
V2	chip_sw_csrng_fuse_en_sw_app_read	chip_sw_csrng_fuse_en_sw_app_read_test	11.009s		0	1	0.00
V2	chip_sw_csrng_known_answer_tests	chip_sw_csrng_kat_test	3.410m	4.171ms	1	1	100.00
V2	chip_sw_edn_entropy_reqs	chip_sw_csrng_edn_concurrency	11.016s		0	1	0.00
		chip_sw_edn_entropy_reqs	10.026s		0	1	0.00
V2	chip_sw_keymgr_dpe_key_derivation	chip_sw_keymgr_dpe_key_derivation	5.491m	6.939ms	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	44.620s	10.200us	0	1	0.00
V2	chip_sw_otbn_op	chip_sw_otbn_ecdsa_op_irq	11.033s		0	1	0.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	11.033s		0	1	0.00
V2	chip_sw_otbn_rnd_entropy	chip_sw_otbn_randomness	4.740m	4.839ms	1	1	100.00
V2	chip_sw_otbn_urnd_entropy	chip_sw_otbn_randomness	4.740m	4.839ms	1	1	100.00
V2	chip_sw_otbn_idle	chip_sw_otbn_randomness	4.740m	4.839ms	1	1	100.00
V2	chip_sw_otbn_mem_scramble	chip_sw_otbn_mem_scramble	11.033s		0	1	0.00
V2	chip_sw_rom_access	chip_sw_rom_ctrl_integrity_check	7.633m	11.740ms	1	1	100.00
V2	chip_sw_rom_ctrl_integrity_check	chip_sw_rom_ctrl_integrity_check	7.633m	11.740ms	1	1	100.00
V2	chip_sw_sram_scrambled_access	chip_sw_sram_ctrl_scrambled_access	10.026s		0	1	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	10.039s		0	1	0.00
V2	chip_sw_sram_execution	chip_sw_sram_ctrl_execution_main	10.032s		0	1	0.00
V2	chip_sw_sram_lc_escalation	chip_sw_all_escalation_resets	10.021s		0	1	0.00
		chip_sw_data_integrity_escalation	10.040s		0	1	0.00
V2	chip_otp_ctrl_init	chip_sw_lc_ctrl_transition	11.051s		0	1	0.00
V2	chip_sw_otp_ctrl_keys	chip_sw_otbn_mem_scramble	11.033s		0	1	0.00
		chip_sw_keymgr_dpe_key_derivation	5.491m	6.939ms	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access	10.026s		0	1	0.00
		chip_sw_rv_core_ibex_icache_invalidate	11.022s		0	1	0.00
V2	chip_sw_otp_ctrl_entropy	chip_sw_otbn_mem_scramble	11.033s		0	1	0.00
		chip_sw_keymgr_dpe_key_derivation	5.491m	6.939ms	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access	10.026s		0	1	0.00
		chip_sw_rv_core_ibex_icache_invalidate	11.022s		0	1	0.00
V2	chip_sw_otp_ctrl_program	chip_sw_lc_ctrl_transition	11.051s		0	1	0.00
V2	chip_sw_otp_ctrl_program_error	chip_sw_lc_ctrl_program_error	11.026s		0	1	0.00
V2	chip_sw_otp_ctrl_hw_cfg	chip_sw_lc_ctrl_otp_hw_cfg	2.069m		0	1	0.00
V2	chip_sw_otp_ctrl_lc_signals	chip_sw_otp_ctrl_lc_signals_test_unlocked0	1.969m		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_dev	1.651m		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_prod	1.485m		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_rma	1.401m		0	1	0.00
		chip_sw_lc_ctrl_transition	11.051s		0	1	0.00
		chip_prim_tl_access	8.847m	13.660ms	1	1	100.00
V2	chip_sw_otp_prim_tl_access	chip_prim_tl_access	8.847m	13.660ms	1	1	100.00
V2	chip_sw_otp_ctrl_nvm_cnt	chip_sw_otp_ctrl_nvm_cnt	11.045s		0	1	0.00
V2	chip_sw_otp_ctrl_sw_parts	chip_sw_otp_ctrl_sw_parts	11.044s		0	1	0.00
V2	chip_sw_ast_clk_outputs	chip_sw_ast_clk_outputs	11.029s		0	1	0.00
V2	chip_sw_ast_sys_clk_jitter	chip_sw_otbn_ecdsa_op_irq_jitter_en	11.033s		0	1	0.00
		chip_sw_aes_enc_jitter_en	41.910s	10.200us	0	1	0.00
		chip_sw_edn_entropy_reqs_jitter	11.052s		0	1	0.00
		chip_sw_hmac_enc_jitter_en	11.050s		0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	44.620s	10.200us	0	1	0.00
		chip_sw_kmac_mode_kmac_jitter_en	43.530s	10.200us	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	10.039s		0	1	0.00
		chip_sw_clkmgr_jitter	2.974m	4.046ms	1	1	100.00
V2	chip_sw_ast_alerts	chip_sw_sensor_ctrl_alert	10.029s		0	1	0.00
V2	chip_sw_sensor_ctrl_ast_alerts	chip_sw_sensor_ctrl_alert	10.029s		0	1	0.00
		chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	10.025s		0	1	0.00
V2	chip_sw_sensor_ctrl_ast_status	chip_sw_sensor_ctrl_status	10.029s		0	1	0.00
V2	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	10.025s		0	1	0.00
V2	chip_sw_soc_proxy_external_reset_requests	chip_sw_soc_proxy_smoketest	10.024s		0	1	0.00
V2	chip_sw_soc_proxy_external_irqs	chip_sw_soc_proxy_smoketest	10.024s		0	1	0.00
V2	chip_sw_soc_proxy_external_alerts	chip_sw_soc_proxy_external_alerts	11.024s		0	1	0.00
V2	chip_sw_soc_proxy_external_wakeup_requests	chip_sw_soc_proxy_external_wakeup	10.024s		0	1	0.00
V2	chip_sw_soc_proxy_gpios	chip_sw_soc_proxy_gpios	10.023s		0	1	0.00
V2	chip_sw_nmi_irq	chip_sw_rv_core_ibex_nmi_irq	12.025s		0	1	0.00
V2	chip_sw_rv_core_ibex_rnd	chip_sw_rv_core_ibex_rnd	3.617m	4.445ms	1	1	100.00
V2	chip_sw_rv_core_ibex_address_translation	chip_sw_rv_core_ibex_address_translation	3.605m	4.494ms	1	1	100.00
V2	chip_sw_rv_core_ibex_icache_scrambled_access	chip_sw_rv_core_ibex_icache_invalidate	11.022s		0	1	0.00
V2	chip_sw_rv_core_ibex_fault_dump	chip_sw_rstmgr_cpu_info	12.908m	20.027ms	0	1	0.00
V2	chip_sw_rv_core_ibex_double_fault	chip_sw_rstmgr_cpu_info	12.908m	20.027ms	0	1	0.00
V2	chip_sw_smoketest	chip_sw_aes_smoketest	11.065s		0	1	0.00
		chip_sw_aon_timer_smoketest	11.062s		0	1	0.00
		chip_sw_clkmgr_smoketest	11.060s		0	1	0.00
		chip_sw_csrng_smoketest	11.058s		0	1	0.00
		chip_sw_gpio_smoketest	13.085s		0	1	0.00
		chip_sw_hmac_smoketest	11.076s		0	1	0.00
		chip_sw_kmac_smoketest	11.074s		0	1	0.00
		chip_sw_otbn_smoketest	11.071s		0	1	0.00
		chip_sw_otp_ctrl_smoketest	11.067s		0	1	0.00
		chip_sw_rv_plic_smoketest	18.064s		0	1	0.00
		chip_sw_rv_timer_smoketest	3.861m	6.170ms	1	1	100.00
		chip_sw_rstmgr_smoketest	16.043s		0	1	0.00
		chip_sw_sram_ctrl_smoketest	10.027s		0	1	0.00
		chip_sw_uart_smoketest	2.817m	4.322ms	1	1	100.00
V2	chip_sw_rom_functests	rom_keymgr_functest	12.076s		0	1	0.00
V2	chip_sw_signed	chip_sw_uart_smoketest_signed	13.081s		0	1	0.00
V2	chip_sw_boot	chip_sw_uart_tx_rx_bootstrap	10.053s		0	1	0.00
V2	chip_sw_secure_boot	base_rom_e2e_smoke	12.549s		0	1	0.00
V2	chip_lc_scrap	chip_sw_lc_ctrl_rma_to_scrap	3.165m	4.656ms	1	1	100.00
		chip_sw_lc_ctrl_raw_to_scrap	3.065m	4.656ms	1	1	100.00
		chip_sw_lc_ctrl_test_locked0_to_scrap	3.039m	4.656ms	1	1	100.00
		chip_sw_lc_ctrl_rand_to_scrap	3.097m	4.656ms	1	1	100.00
V2	chip_lc_test_locked	chip_sw_lc_walkthrough_testunlocks	10.033s		0	1	0.00
		chip_rv_dm_lc_disabled	10.084m	17.314ms	1	1	100.00
V2	chip_sw_lc_walkthrough	chip_sw_lc_walkthrough_dev	11.184s		0	1	0.00
		chip_sw_lc_walkthrough_prod	11.182s		0	1	0.00
		chip_sw_lc_walkthrough_prodend	11.186s		0	1	0.00
		chip_sw_lc_walkthrough_rma	11.046s		0	1	0.00
		chip_sw_lc_walkthrough_testunlocks	10.033s		0	1	0.00
V2	chip_sw_lc_ctrl_volatile_raw_unlock	chip_sw_lc_ctrl_volatile_raw_unlock	11.182s		0	1	0.00
		chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	11.040s		0	1	0.00
		rom_volatile_raw_unlock	10.074s		0	1	0.00
V2	chip_sw_rom_raw_unlock	rom_raw_unlock	10.082s		0	1	0.00
V2	chip_sw_exit_test_unlocked_bootstrap	chip_sw_exit_test_unlocked_bootstrap	10.052s		0	1	0.00
V2	chip_sw_inject_scramble_seed	chip_sw_inject_scramble_seed	10.054s		0	1	0.00
V2	tl_d_oob_addr_access	chip_tl_errors	2.485m	3.702ms	0	1	0.00
V2	tl_d_illegal_access	chip_tl_errors	2.485m	3.702ms	0	1	0.00
V2	tl_d_outstanding_access	chip_csr_aliasing	2.336m	3.702ms	0	1	0.00
		chip_same_csr_outstanding	2.373m	3.702ms	0	1	0.00
		chip_csr_hw_reset	2.362m	3.702ms	0	1	0.00
		chip_csr_rw	2.425m	3.702ms	0	1	0.00
V2	tl_d_partial_access	chip_csr_aliasing	2.336m	3.702ms	0	1	0.00
		chip_same_csr_outstanding	2.373m	3.702ms	0	1	0.00
		chip_csr_hw_reset	2.362m	3.702ms	0	1	0.00
		chip_csr_rw	2.425m	3.702ms	0	1	0.00
V2	xbar_base_random_sequence	xbar_random	3.030m	510.675us	1	1	100.00
V2	xbar_random_delay	xbar_smoke_zero_delays	7.840s	10.734us	1	1	100.00
		xbar_smoke_large_delays	3.657m	2.073ms	1	1	100.00
		xbar_smoke_slow_rsp	4.352m	1.822ms	1	1	100.00
		xbar_random_zero_delays	1.406m	74.809us	1	1	100.00
		xbar_random_large_delays	22.236m	12.543ms	1	1	100.00
		xbar_random_slow_rsp	35.393m	14.519ms	1	1	100.00
V2	xbar_unmapped_address	xbar_unmapped_addr	1.730m	221.078us	1	1	100.00
		xbar_error_and_unmapped_addr	1.507m	221.797us	1	1	100.00
V2	xbar_error_cases	xbar_error_random	2.593m	510.675us	1	1	100.00
		xbar_error_and_unmapped_addr	1.507m	221.797us	1	1	100.00
V2	xbar_all_access_same_device	xbar_access_same_device	4.659m	835.777us	1	1	100.00
		xbar_access_same_device_slow_rsp	57.841m	24.061ms	1	1	100.00
V2	xbar_all_hosts_use_same_source_id	xbar_same_source	59.510s	199.661us	1	1	100.00
V2	xbar_stress_all	xbar_stress_all	10.621m	1.684ms	1	1	100.00
		xbar_stress_all_with_error	9.396m	1.684ms	1	1	100.00
V2	xbar_stress_with_reset	xbar_stress_all_with_rand_reset	27.032m	2.777ms	1	1	100.00
		xbar_stress_all_with_reset_error	22.385m	2.777ms	1	1	100.00
V2	rom_e2e_smoke	rom_e2e_smoke	11.022s		0	1	0.00
V2	rom_e2e_shutdown_output	rom_e2e_shutdown_output	10.041s		0	1	0.00
V2	rom_e2e_shutdown_exception_c	rom_e2e_shutdown_exception_c	10.032s		0	1	0.00
V2	rom_e2e_boot_policy_valid	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	10.050s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_dev	10.048s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod	10.048s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod_end	11.069s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_rma	10.042s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	10.039s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_dev	10.054s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod	10.058s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	10.059s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_rma	11.052s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	12.067s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_dev	12.065s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod	11.040s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	11.054s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_rma	10.028s		0	1	0.00
V2	rom_e2e_sigverify_always	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	10.059s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_dev	11.059s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod	15.072s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod_end	15.070s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_rma	14.046s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	14.055s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_dev	14.052s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod	14.049s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	12.019s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_rma	10.058s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	10.056s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_dev	10.053s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod	14.065s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	14.063s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_rma	14.060s		0	1	0.00
V2	rom_e2e_asm_init	rom_e2e_asm_init_test_unlocked0	13.043s		0	1	0.00
		rom_e2e_asm_init_dev	14.053s		0	1	0.00
		rom_e2e_asm_init_prod	11.047s		0	1	0.00
		rom_e2e_asm_init_prod_end	10.060s		0	1	0.00
		rom_e2e_asm_init_rma	10.058s		0	1	0.00
V2	rom_e2e_keymgr_init	rom_e2e_keymgr_init_rom_ext_meas	10.143s		0	1	0.00
		rom_e2e_keymgr_init_rom_ext_no_meas	10.141s		0	1	0.00
		rom_e2e_keymgr_init_rom_ext_invalid_meas	10.118s		0	1	0.00
V2	rom_e2e_static_critical	rom_e2e_static_critical	10.121s		0	1	0.00
V2		TOTAL			38	211	18.01
V2S	chip_sw_aes_masking_off	chip_sw_aes_masking_off	11.011s		0	1	0.00
V2S	chip_sw_rv_core_ibex_lockstep_glitch	chip_sw_rv_core_ibex_lockstep_glitch	3.028m	4.046ms	1	1	100.00
V2S		TOTAL			1	2	50.00
V3	chip_rv_dm_perform_debug	rom_e2e_jtag_debug_test_unlocked0	10.101s		0	1	0.00
		rom_e2e_jtag_debug_dev	10.139s		0	1	0.00
		rom_e2e_jtag_debug_rma	10.132s		0	1	0.00
V3	chip_sw_rv_dm_access_after_hw_reset	chip_sw_rv_dm_access_after_escalation_reset	10.058s		0	1	0.00
V3	chip_sw_plic_alerts	chip_sw_all_escalation_resets	10.021s		0	1	0.00
V3	chip_sw_otp_ctrl_vendor_test_csr_access	chip_sw_otp_ctrl_vendor_test_csr_access	11.044s		0	1	0.00
V3	chip_sw_otp_ctrl_escalation	chip_sw_otp_ctrl_escalation	11.042s		0	1	0.00
V3	chip_sw_coremark	chip_sw_coremark	10.027s		0	1	0.00
V3	chip_sw_power_max_load	chip_sw_power_virus	11.025s		0	1	0.00
V3	rom_e2e_debug	rom_e2e_jtag_debug_test_unlocked0	10.101s		0	1	0.00
		rom_e2e_jtag_debug_dev	10.139s		0	1	0.00
		rom_e2e_jtag_debug_rma	10.132s		0	1	0.00
V3	rom_e2e_jtag_inject	rom_e2e_jtag_inject_test_unlocked0	11.154s		0	1	0.00
		rom_e2e_jtag_inject_dev	10.126s		0	1	0.00
		rom_e2e_jtag_inject_rma	10.123s		0	1	0.00
V3	rom_e2e_self_hash	rom_e2e_self_hash	14.086s		0	1	0.00
V3		TOTAL			0	12	0.00
	Unmapped tests	chip_sw_rstmgr_rst_cnsty_escalation	10.029s		0	1	0.00
		chip_sw_mbx_smoketest	3.773m	4.697ms	1	1	100.00
		chip_sw_dma_inline_hashing	3.449m	4.979ms	1	1	100.00
		chip_sw_dma_abort	3.147m	4.440ms	0	1	0.00
		rom_e2e_sigverify_mod_exp_test_unlocked0_otbn	10.118s		0	1	0.00
		rom_e2e_sigverify_mod_exp_test_unlocked0_sw	10.086s		0	1	0.00
		rom_e2e_sigverify_mod_exp_dev_otbn	10.086s		0	1	0.00
		rom_e2e_sigverify_mod_exp_dev_sw	10.081s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_otbn	10.078s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_sw	10.076s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_end_otbn	10.073s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_end_sw	10.085s		0	1	0.00
		rom_e2e_sigverify_mod_exp_rma_otbn	10.080s		0	1	0.00
		rom_e2e_sigverify_mod_exp_rma_sw	10.077s		0	1	0.00
		TOTAL			43	254	16.93

Failure Buckets

Job returned non-zero exit code has 186 failures:

Test chip_sw_example_rom has 1 failures.

0.chip_sw_example_rom.1
Log /nightly/runs/scratch/dj-sw-nightly/chip_darjeeling_asic-sim-vcs/0.chip_sw_example_rom/latest/run.log

  Target //sw/device/tests:example_test_from_rom_sim_dv failed to build
  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests:example_test_from_rom_sim_dv' failed; build aborted: Target //sw/device/tests:example_test_from_rom_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests:example_test_from_rom_sim_dv (7e736f)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 3.974s, Critical Path: 0.21s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_example_manufacturer has 1 failures.

0.chip_sw_example_manufacturer.1
Log /nightly/runs/scratch/dj-sw-nightly/chip_darjeeling_asic-sim-vcs/0.chip_sw_example_manufacturer/latest/run.log

  Analyzing: target @@+hooks+manufacturer_test_hooks//:example_test_sim_dv (1 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '@@+hooks+manufacturer_test_hooks//:example_test_sim_dv' failed; build aborted: Target @@+hooks+manufacturer_test_hooks//:example_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      @@+hooks+manufacturer_test_hooks//:example_test_sim_dv (7e736f)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 0.204s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_example_concurrency has 1 failures.

0.chip_sw_example_concurrency.1
Log /nightly/runs/scratch/dj-sw-nightly/chip_darjeeling_asic-sim-vcs/0.chip_sw_example_concurrency/latest/run.log

  Analyzing: target //sw/device/tests:example_concurrency_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests:example_concurrency_test_sim_dv' failed; build aborted: Target //sw/device/tests:example_concurrency_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests:example_concurrency_test_sim_dv (7e736f)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 0.583s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_all_escalation_resets has 1 failures.

0.chip_sw_all_escalation_resets.1
Log /nightly/runs/scratch/dj-sw-nightly/chip_darjeeling_asic-sim-vcs/0.chip_sw_all_escalation_resets/latest/run.log

  Analyzing: target //sw/device/tests/sim_dv:all_escalation_resets_test_sim_dv (1 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests/sim_dv:all_escalation_resets_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:all_escalation_resets_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests/sim_dv:all_escalation_resets_test_sim_dv (7e736f)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 0.086s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_rstmgr_rst_cnsty_escalation has 1 failures.

0.chip_sw_rstmgr_rst_cnsty_escalation.1
Log /nightly/runs/scratch/dj-sw-nightly/chip_darjeeling_asic-sim-vcs/0.chip_sw_rstmgr_rst_cnsty_escalation/latest/run.log

  Analyzing: target //sw/device/tests/sim_dv:all_escalation_resets_test_sim_dv (0 packages loaded, 0 targets configured)
  [0 / 1] checking cached actions
  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests/sim_dv:all_escalation_resets_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:all_escalation_resets_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests/sim_dv:all_escalation_resets_test_sim_dv (7e736f)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 0.064s, Critical Path: 0.00s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

... and 181 more tests.

UVM_FATAL @ * us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat" has 6 failures:
- Test chip_sw_aes_enc_jitter_en has 1 failures.
  - 0.chip_sw_aes_enc_jitter_en.1
    Line 394, in log /nightly/runs/scratch/dj-sw-nightly/chip_darjeeling_asic-sim-vcs/0.chip_sw_aes_enc_jitter_en/latest/run.log
```
  UVM_FATAL @  10.200001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_keymgr_dpe_key_derivation_jitter_en has 1 failures.
  - 0.chip_sw_keymgr_dpe_key_derivation_jitter_en.1
    Line 389, in log /nightly/runs/scratch/dj-sw-nightly/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation_jitter_en/latest/run.log
```
  UVM_FATAL @  10.200001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_kmac_mode_kmac_jitter_en has 1 failures.
  - 0.chip_sw_kmac_mode_kmac_jitter_en.1
    Line 401, in log /nightly/runs/scratch/dj-sw-nightly/chip_darjeeling_asic-sim-vcs/0.chip_sw_kmac_mode_kmac_jitter_en/latest/run.log
```
  UVM_FATAL @  10.200001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_aes_enc_jitter_en_reduced_freq has 1 failures.
  - 0.chip_sw_aes_enc_jitter_en_reduced_freq.1
    Line 390, in log /nightly/runs/scratch/dj-sw-nightly/chip_darjeeling_asic-sim-vcs/0.chip_sw_aes_enc_jitter_en_reduced_freq/latest/run.log
```
  UVM_FATAL @  10.200001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_keymgr_dpe_key_derivation_jitter_en_reduced_freq has 1 failures.
  - 0.chip_sw_keymgr_dpe_key_derivation_jitter_en_reduced_freq.1
    Line 390, in log /nightly/runs/scratch/dj-sw-nightly/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation_jitter_en_reduced_freq/latest/run.log
```
  UVM_FATAL @  10.200001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- ... and 1 more tests.

UVM_ERROR @ * us: (tl_monitor.sv:178) monitor [monitor] Number of pending a_req exceeds limit * has 5 failures:

Test chip_csr_aliasing has 1 failures.

0.chip_csr_aliasing.1
Line 240, in log /nightly/runs/scratch/dj-sw-nightly/chip_darjeeling_asic-sim-vcs/0.chip_csr_aliasing/latest/run.log

  UVM_ERROR @ 3702.295880 us: (tl_monitor.sv:178) uvm_test_top.env.m_tl_agent_chip_reg_block.monitor [uvm_test_top.env.m_tl_agent_chip_reg_block.monitor] Number of pending a_req exceeds limit 4
  UVM_INFO @ 3702.295880 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_same_csr_outstanding has 1 failures.

0.chip_same_csr_outstanding.1
Line 240, in log /nightly/runs/scratch/dj-sw-nightly/chip_darjeeling_asic-sim-vcs/0.chip_same_csr_outstanding/latest/run.log

  UVM_ERROR @ 3701.885880 us: (tl_monitor.sv:178) uvm_test_top.env.m_tl_agent_chip_reg_block.monitor [uvm_test_top.env.m_tl_agent_chip_reg_block.monitor] Number of pending a_req exceeds limit 4
  UVM_INFO @ 3701.885880 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_tl_errors has 1 failures.

0.chip_tl_errors.1
Line 240, in log /nightly/runs/scratch/dj-sw-nightly/chip_darjeeling_asic-sim-vcs/0.chip_tl_errors/latest/run.log

  UVM_ERROR @ 3701.965880 us: (tl_monitor.sv:178) uvm_test_top.env.m_tl_agent_chip_reg_block.monitor [uvm_test_top.env.m_tl_agent_chip_reg_block.monitor] Number of pending a_req exceeds limit 4
  UVM_INFO @ 3701.965880 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_csr_hw_reset has 1 failures.

0.chip_csr_hw_reset.1
Line 249, in log /nightly/runs/scratch/dj-sw-nightly/chip_darjeeling_asic-sim-vcs/0.chip_csr_hw_reset/latest/run.log

  UVM_ERROR @ 3702.395880 us: (tl_monitor.sv:178) uvm_test_top.env.m_tl_agent_chip_reg_block.monitor [uvm_test_top.env.m_tl_agent_chip_reg_block.monitor] Number of pending a_req exceeds limit 4
  UVM_INFO @ 3702.395880 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_csr_rw has 1 failures.

0.chip_csr_rw.1
Line 240, in log /nightly/runs/scratch/dj-sw-nightly/chip_darjeeling_asic-sim-vcs/0.chip_csr_rw/latest/run.log

  UVM_ERROR @ 3702.395880 us: (tl_monitor.sv:178) uvm_test_top.env.m_tl_agent_chip_reg_block.monitor [uvm_test_top.env.m_tl_agent_chip_reg_block.monitor] Number of pending a_req exceeds limit 4
  UVM_INFO @ 3702.395880 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (chip_sw_base_vseq.sv:374) virtual_sequencer [chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInBootRom, TIMEOUT = * ns has 5 failures:

Test chip_sw_rstmgr_sw_req has 1 failures.

0.chip_sw_rstmgr_sw_req.1
Line 395, in log /nightly/runs/scratch/dj-sw-nightly/chip_darjeeling_asic-sim-vcs/0.chip_sw_rstmgr_sw_req/latest/run.log

  UVM_ERROR @ 12026.586846 us: (chip_sw_base_vseq.sv:374) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInBootRom, TIMEOUT = 12000000 ns

  UVM_INFO @ 12026.586846 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_rstmgr_cpu_info has 1 failures.

0.chip_sw_rstmgr_cpu_info.1
Line 394, in log /nightly/runs/scratch/dj-sw-nightly/chip_darjeeling_asic-sim-vcs/0.chip_sw_rstmgr_cpu_info/latest/run.log

  UVM_ERROR @ 20026.586846 us: (chip_sw_base_vseq.sv:374) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInBootRom, TIMEOUT = 20000000 ns

  UVM_INFO @ 20026.586846 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_aes_entropy has 1 failures.

0.chip_sw_aes_entropy.1
Line 393, in log /nightly/runs/scratch/dj-sw-nightly/chip_darjeeling_asic-sim-vcs/0.chip_sw_aes_entropy/latest/run.log

  UVM_ERROR @ 15026.586846 us: (chip_sw_base_vseq.sv:374) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInBootRom, TIMEOUT = 15000000 ns

  UVM_INFO @ 15026.586846 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_kmac_mode_cshake has 1 failures.

0.chip_sw_kmac_mode_cshake.1
Line 397, in log /nightly/runs/scratch/dj-sw-nightly/chip_darjeeling_asic-sim-vcs/0.chip_sw_kmac_mode_cshake/latest/run.log

  UVM_ERROR @ 12026.586846 us: (chip_sw_base_vseq.sv:374) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInBootRom, TIMEOUT = 12000000 ns

  UVM_INFO @ 12026.586846 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_kmac_mode_kmac has 1 failures.

0.chip_sw_kmac_mode_kmac.1
Line 403, in log /nightly/runs/scratch/dj-sw-nightly/chip_darjeeling_asic-sim-vcs/0.chip_sw_kmac_mode_kmac/latest/run.log

  UVM_ERROR @ 12026.586846 us: (chip_sw_base_vseq.sv:374) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInBootRom, TIMEOUT = 12000000 ns

  UVM_INFO @ 12026.586846 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:489) [chip_sw_keymgr_dpe_key_derivation_vseq] Check failed keymgr_pkg::KeyWidth'(get_kmac_digest(kmac_key, data_arr)) == act_digest (* [*] vs * [*]) has 2 failures:

Test chip_sw_keymgr_dpe_key_derivation has 1 failures.

0.chip_sw_keymgr_dpe_key_derivation.1
Line 445, in log /nightly/runs/scratch/dj-sw-nightly/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation/latest/run.log

  UVM_ERROR @ 6938.782138 us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:489) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_dpe_key_derivation_vseq] Check failed keymgr_pkg::KeyWidth'(get_kmac_digest(kmac_key, data_arr)) == act_digest (96846920872675169919696822363017883226346916629245559711877789681648821960210 [0xd61d6a29c2b9cbb43e7e5fdd2632a5b55378fd15487ec52262cbf36c2aa17e12] vs 97859825677027007224150690175145672742935591554333099125277249837138277731050 [0xd85ab2d11074471fca5b46e3b39f31184fd8c272f3bae70f9b70062315128aea])
  UVM_INFO @ 6938.782138 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_keymgr_dpe_key_derivation_prod has 1 failures.

0.chip_sw_keymgr_dpe_key_derivation_prod.1
Line 451, in log /nightly/runs/scratch/dj-sw-nightly/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation_prod/latest/run.log

  UVM_ERROR @ 6938.782138 us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:489) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_dpe_key_derivation_vseq] Check failed keymgr_pkg::KeyWidth'(get_kmac_digest(kmac_key, data_arr)) == act_digest (95080306937948662591230339866174416105155358842050874919283309046695081638149 [0xd2358bf108ed4b9e30794d2bb8db8f644c7af100f2c2abf94efe4b10a5457905] vs 43624048373203516635894345205542958669503153251670028163140794487979745328631 [0x6072561d700e78e4f6f05219d25ff338ce9ec0f7f5a90ca8f82669d38999bdf7])
  UVM_INFO @ 6938.782138 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:519) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@44254) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 2 failures:

Test chip_jtag_csr_rw has 1 failures.

0.chip_jtag_csr_rw.1
Line 5613, in log /nightly/runs/scratch/dj-sw-nightly/chip_darjeeling_asic-sim-vcs/0.chip_jtag_csr_rw/latest/run.log

  UVM_ERROR @ 3683.408174 us: (cip_base_scoreboard.sv:519) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@44254) { a_addr: 'h30480000  a_data: 'h1f135537  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h1b  a_opcode: 'h1  a_user: 'h248d9  d_param: 'h0  d_source: 'h1b  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_source_is_overridden: 'h0  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 1, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 3683.408174 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_jtag_mem_access has 1 failures.

0.chip_jtag_mem_access.1
Line 5613, in log /nightly/runs/scratch/dj-sw-nightly/chip_darjeeling_asic-sim-vcs/0.chip_jtag_mem_access/latest/run.log

  UVM_ERROR @ 3683.408174 us: (cip_base_scoreboard.sv:519) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@44254) { a_addr: 'h30480000  a_data: 'h1f135537  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h1b  a_opcode: 'h1  a_user: 'h248d9  d_param: 'h0  d_source: 'h1b  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_source_is_overridden: 'h0  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 1, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 3683.408174 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty has 1 failures:
- Test chip_sw_spi_device_pass_through_collision has 1 failures.
  - 0.chip_sw_spi_device_pass_through_collision.1
    Line 640, in log /nightly/runs/scratch/dj-sw-nightly/chip_darjeeling_asic-sim-vcs/0.chip_sw_spi_device_pass_through_collision/latest/run.log
```
  UVM_ERROR @ 4503.649986 us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty
  UVM_INFO @ 4503.649986 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[RamCtn0]] file kmac_app_rom_test_sim_dv.*.vmem could not be opened for r mode has 1 failures:
- Test chip_sw_kmac_app_rom has 1 failures.
  - 0.chip_sw_kmac_app_rom.1
    Line 419, in log /nightly/runs/scratch/dj-sw-nightly/chip_darjeeling_asic-sim-vcs/0.chip_sw_kmac_app_rom/latest/run.log
```
  UVM_FATAL @  10.200001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[RamCtn0]] file kmac_app_rom_test_sim_dv.32.vmem could not be opened for r mode
  UVM_INFO @  10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Error-[CNST-CIF] Constraints inconsistency failure has 1 failures:
- Test chip_padctrl_attributes has 1 failures.
  - 0.chip_padctrl_attributes.1
    Line 287, in log /nightly/runs/scratch/dj-sw-nightly/chip_darjeeling_asic-sim-vcs/0.chip_padctrl_attributes/latest/run.log
```
  Error-[CNST-CIF] Constraints inconsistency failure
  ../src/lowrisc_dv_dv_lib_0/dv_base_test.sv, 95
    Constraints are inconsistent and cannot be solved.
    Please check the inconsistent constraints being printed above and rewrite
    them.
```

UVM_FATAL @ * us: sequencer [sequencer] Item_done() called with no outstanding requests. Each call to item_done() must be paired with a previous call to get_next_item(). has 1 failures:

Test chip_sw_dma_abort has 1 failures.

0.chip_sw_dma_abort.1
Line 403, in log /nightly/runs/scratch/dj-sw-nightly/chip_darjeeling_asic-sim-vcs/0.chip_sw_dma_abort/latest/run.log

  UVM_FATAL @ 4439.696698 us: uvm_test_top.env.m_spi_device_agents0.sequencer [uvm_test_top.env.m_spi_device_agents0.sequencer] Item_done() called with no outstanding requests. Each call to item_done() must be paired with a previous call to get_next_item().
  UVM_INFO @ 4439.696698 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Offending '(tl_h_i[*].a_source[(IDW - *)-:STIDW] == '0)' has 1 failures:
- Test chip_csr_mem_rw_with_rand_reset has 1 failures.
  - 0.chip_csr_mem_rw_with_rand_reset.1
    Line 246, in log /nightly/runs/scratch/dj-sw-nightly/chip_darjeeling_asic-sim-vcs/0.chip_csr_mem_rw_with_rand_reset/latest/run.log
```
      Offending '(tl_h_i[0].a_source[(IDW - 1)-:STIDW] == '0)'
  UVM_ERROR @ 3701.755880 us: (tlul_socket_m1.sv:101) [ASSERT FAILED] idInRange
  UVM_INFO @ 3701.755880 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```