AES/UNMASKED Simulation Results

Tuesday March 18 2025 17:10:07 UTC

GitHub Revision: 6ff667cbce

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	4.000s	112.810us	1	1	100.00
V1	smoke	aes_smoke	4.000s	102.810us	1	1	100.00
V1	csr_hw_reset	aes_csr_hw_reset	3.000s	69.722us	1	1	100.00
V1	csr_rw	aes_csr_rw	3.000s	68.840us	1	1	100.00
V1	csr_bit_bash	aes_csr_bit_bash	6.000s	671.191us	1	1	100.00
V1	csr_aliasing	aes_csr_aliasing	4.000s	195.297us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	3.000s	4.874us	0	1	0.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	3.000s	68.840us	1	1	100.00
		aes_csr_aliasing	4.000s	195.297us	1	1	100.00
V1		TOTAL			6	7	85.71
V2	algorithm	aes_smoke	4.000s	102.810us	1	1	100.00
		aes_config_error	5.000s	150.516us	1	1	100.00
		aes_stress	4.000s	95.416us	1	1	100.00
V2	key_length	aes_smoke	4.000s	102.810us	1	1	100.00
		aes_config_error	5.000s	150.516us	1	1	100.00
		aes_stress	4.000s	95.416us	1	1	100.00
V2	back2back	aes_stress	4.000s	95.416us	1	1	100.00
		aes_b2b	6.000s	196.996us	1	1	100.00
V2	backpressure	aes_stress	4.000s	95.416us	1	1	100.00
V2	multi_message	aes_smoke	4.000s	102.810us	1	1	100.00
		aes_config_error	5.000s	150.516us	1	1	100.00
		aes_stress	4.000s	95.416us	1	1	100.00
		aes_alert_reset	5.000s	186.516us	1	1	100.00
V2	failure_test	aes_man_cfg_err	4.000s	111.221us	1	1	100.00
		aes_config_error	5.000s	150.516us	1	1	100.00
		aes_alert_reset	5.000s	186.516us	1	1	100.00
V2	trigger_clear_test	aes_clear	5.000s	130.516us	1	1	100.00
V2	nist_test_vectors	aes_nist_vectors	6.000s	441.342us	1	1	100.00
V2	reset_recovery	aes_alert_reset	5.000s	186.516us	1	1	100.00
V2	stress	aes_stress	4.000s	95.416us	1	1	100.00
V2	sideload	aes_stress	4.000s	95.416us	1	1	100.00
		aes_sideload	4.000s	108.810us	1	1	100.00
V2	deinitialization	aes_deinit	5.000s	124.516us	1	1	100.00
V2	stress_all	aes_stress_all	8.000s	639.920us	1	1	100.00
V2	alert_test	aes_alert_test	3.000s	73.230us	1	1	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	3.000s	5.790us	0	1	0.00
V2	tl_d_illegal_access	aes_tl_errors	3.000s	5.790us	0	1	0.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	3.000s	69.722us	1	1	100.00
		aes_csr_rw	3.000s	68.840us	1	1	100.00
		aes_csr_aliasing	4.000s	195.297us	1	1	100.00
		aes_same_csr_outstanding	4.000s	114.433us	1	1	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	3.000s	69.722us	1	1	100.00
		aes_csr_rw	3.000s	68.840us	1	1	100.00
		aes_csr_aliasing	4.000s	195.297us	1	1	100.00
		aes_same_csr_outstanding	4.000s	114.433us	1	1	100.00
V2		TOTAL			12	13	92.31
V2S	reseeding	aes_reseed	5.000s	118.484us	1	1	100.00
V2S	fault_inject	aes_fi	5.000s	186.398us	1	1	100.00
		aes_control_fi			0	1	0.00
		aes_cipher_fi	4.000s	53.221us	1	1	100.00
V2S	shadow_reg_update_error	aes_shadow_reg_errors	3.000s	33.041us	0	1	0.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	3.000s	33.041us	0	1	0.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	3.000s	33.041us	0	1	0.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	3.000s	33.041us	0	1	0.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	4.000s	76.852us	0	1	0.00
V2S	tl_intg_err	aes_sec_cm	5.000s	696.902us	1	1	100.00
		aes_tl_intg_err	4.000s	207.483us	1	1	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	4.000s	207.483us	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	5.000s	186.516us	1	1	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	3.000s	33.041us	0	1	0.00
V2S	sec_cm_main_config_sparse	aes_smoke	4.000s	102.810us	1	1	100.00
		aes_stress	4.000s	95.416us	1	1	100.00
		aes_alert_reset	5.000s	186.516us	1	1	100.00
		aes_core_fi	5.000s	148.516us	1	1	100.00
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	3.000s	33.041us	0	1	0.00
V2S	sec_cm_aux_config_regwen	aes_readability	4.000s	87.633us	1	1	100.00
		aes_stress	4.000s	95.416us	1	1	100.00
V2S	sec_cm_key_sideload	aes_stress	4.000s	95.416us	1	1	100.00
		aes_sideload	4.000s	108.810us	1	1	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	4.000s	87.633us	1	1	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	4.000s	87.633us	1	1	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	4.000s	87.633us	1	1	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	4.000s	87.633us	1	1	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	4.000s	87.633us	1	1	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	4.000s	95.416us	1	1	100.00
V2S	sec_cm_key_masking	aes_stress	4.000s	95.416us	1	1	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	5.000s	186.398us	1	1	100.00
V2S	sec_cm_main_fsm_redun	aes_fi	5.000s	186.398us	1	1	100.00
		aes_control_fi			0	1	0.00
		aes_cipher_fi	4.000s	53.221us	1	1	100.00
		aes_ctr_fi	5.000s	77.339us	1	1	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	5.000s	186.398us	1	1	100.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	5.000s	186.398us	1	1	100.00
		aes_control_fi			0	1	0.00
		aes_cipher_fi	4.000s	53.221us	1	1	100.00
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	4.000s	53.221us	1	1	100.00
V2S	sec_cm_ctr_fsm_sparse	aes_fi	5.000s	186.398us	1	1	100.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	5.000s	186.398us	1	1	100.00
		aes_control_fi			0	1	0.00
		aes_ctr_fi	5.000s	77.339us	1	1	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	5.000s	186.398us	1	1	100.00
		aes_control_fi			0	1	0.00
		aes_cipher_fi	4.000s	53.221us	1	1	100.00
		aes_ctr_fi	5.000s	77.339us	1	1	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	5.000s	186.516us	1	1	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	5.000s	186.398us	1	1	100.00
		aes_control_fi			0	1	0.00
		aes_cipher_fi	4.000s	53.221us	1	1	100.00
		aes_ctr_fi	5.000s	77.339us	1	1	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	5.000s	186.398us	1	1	100.00
		aes_control_fi			0	1	0.00
		aes_cipher_fi	4.000s	53.221us	1	1	100.00
		aes_ctr_fi	5.000s	77.339us	1	1	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	5.000s	186.398us	1	1	100.00
		aes_control_fi			0	1	0.00
		aes_ctr_fi	5.000s	77.339us	1	1	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	5.000s	186.398us	1	1	100.00
		aes_control_fi			0	1	0.00
		aes_cipher_fi	4.000s	53.221us	1	1	100.00
V2S		TOTAL			8	11	72.73
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	3.000s	4.874us	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			26	32	81.25

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:298) [aes_common_vseq] Check failed rsp.d_error == exp_err_rsp (* [*] vs * [*]) unexpected error response for addr: * has 3 failures:

  • Test aes_stress_all_with_rand_reset has 1 failures.

    • 0.aes_stress_all_with_rand_reset.1
      Line 104, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @   4874389 ps: (cip_base_vseq.sv:298) [uvm_test_top.env.virtual_sequencer.aes_common_vseq] Check failed rsp.d_error == exp_err_rsp (0 [0x0] vs 1 [0x1]) unexpected error response for addr: 0xbf5e6074
        UVM_INFO @   4874389 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test aes_tl_errors has 1 failures.

    • 0.aes_tl_errors.1
      Line 103, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/0.aes_tl_errors/latest/run.log

        UVM_ERROR @   5789635 ps: (cip_base_vseq.sv:298) [uvm_test_top.env.virtual_sequencer.aes_common_vseq] Check failed rsp.d_error == exp_err_rsp (0 [0x0] vs 1 [0x1]) unexpected error response for addr: 0x43ab1904
        UVM_INFO @   5789635 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test aes_csr_mem_rw_with_rand_reset has 1 failures.

    • 0.aes_csr_mem_rw_with_rand_reset.1
      Line 104, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/0.aes_csr_mem_rw_with_rand_reset/latest/run.log

        UVM_ERROR @   4874389 ps: (cip_base_vseq.sv:298) [uvm_test_top.env.virtual_sequencer.aes_common_vseq] Check failed rsp.d_error == exp_err_rsp (0 [0x0] vs 1 [0x1]) unexpected error response for addr: 0xbf5e6074
        UVM_INFO @   4874389 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (alert_receiver_driver.sv:146) [driver] Check failed (cfg.vif.receiver_cb.alert_tx.alert_p) alert_p not high, despite an item in r_alert_rsp_q has 2 failures:

  • Test aes_shadow_reg_errors has 1 failures.

    • 0.aes_shadow_reg_errors.1
      Line 103, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/0.aes_shadow_reg_errors/latest/run.log

        UVM_FATAL @  33040991 ps: (alert_receiver_driver.sv:146) [uvm_test_top.env.m_alert_agent_fatal_fault.driver] Check failed (cfg.vif.receiver_cb.alert_tx.alert_p) alert_p not high, despite an item in r_alert_rsp_q
        UVM_INFO @  33040991 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test aes_shadow_reg_errors_with_csr_rw has 1 failures.

    • 0.aes_shadow_reg_errors_with_csr_rw.1
      Line 103, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/0.aes_shadow_reg_errors_with_csr_rw/latest/run.log

        UVM_FATAL @  76851758 ps: (alert_receiver_driver.sv:146) [uvm_test_top.env.m_alert_agent_fatal_fault.driver] Check failed (cfg.vif.receiver_cb.alert_tx.alert_p) alert_p not high, despite an item in r_alert_rsp_q
        UVM_INFO @  76851758 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Job timed out after * minutes has 1 failures:

  • Test aes_control_fi has 1 failures.

    • 0.aes_control_fi.1
      Log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/0.aes_control_fi/latest/run.log

        Job timed out after 1 minutes