AON_TIMER Simulation Results

Tuesday March 18 2025 17:10:07 UTC

GitHub Revision: 6ff667cbce

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	aon_timer_smoke	1.620s	563.540us	1	1	100.00
V1	csr_hw_reset	aon_timer_csr_hw_reset	1.690s	1.178ms	1	1	100.00
V1	csr_rw	aon_timer_csr_rw	1.460s	418.788us	1	1	100.00
V1	csr_bit_bash	aon_timer_csr_bit_bash	5.180s	11.879ms	1	1	100.00
V1	csr_aliasing	aon_timer_csr_aliasing	1.760s	568.081us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	aon_timer_csr_mem_rw_with_rand_reset	1.610s	347.079us	0	1	0.00
V1	regwen_csr_and_corresponding_lockable_csr	aon_timer_csr_rw	1.460s	418.788us	1	1	100.00
		aon_timer_csr_aliasing	1.760s	568.081us	1	1	100.00
V1	mem_walk	aon_timer_mem_walk	1.510s	378.538us	1	1	100.00
V1	mem_partial_access	aon_timer_mem_partial_access	1.600s	377.205us	1	1	100.00
V1		TOTAL			7	8	87.50
V2	prescaler	aon_timer_prescaler	5.480s	15.544ms	1	1	100.00
V2	jump	aon_timer_jump	1.580s	610.040us	1	1	100.00
V2	stress_all	aon_timer_stress_all	28.670s	102.106ms	1	1	100.00
V2	intr_test	aon_timer_intr_test	1.570s	382.246us	1	1	100.00
V2	tl_d_oob_addr_access	aon_timer_tl_errors	1.450s	347.038us	0	1	0.00
V2	tl_d_illegal_access	aon_timer_tl_errors	1.450s	347.038us	0	1	0.00
V2	tl_d_outstanding_access	aon_timer_csr_hw_reset	1.690s	1.178ms	1	1	100.00
		aon_timer_csr_rw	1.460s	418.788us	1	1	100.00
		aon_timer_csr_aliasing	1.760s	568.081us	1	1	100.00
		aon_timer_same_csr_outstanding	2.190s	2.552ms	1	1	100.00
V2	tl_d_partial_access	aon_timer_csr_hw_reset	1.690s	1.178ms	1	1	100.00
		aon_timer_csr_rw	1.460s	418.788us	1	1	100.00
		aon_timer_csr_aliasing	1.760s	568.081us	1	1	100.00
		aon_timer_same_csr_outstanding	2.190s	2.552ms	1	1	100.00
V2		TOTAL			5	6	83.33
V2S	tl_intg_err	aon_timer_sec_cm	3.660s	7.354ms	1	1	100.00
		aon_timer_tl_intg_err	4.080s	8.015ms	1	1	100.00
V2S	sec_cm_bus_integrity	aon_timer_tl_intg_err	4.080s	8.015ms	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	max_threshold	aon_timer_smoke_max_thold	1.450s	588.540us	1	1	100.00
V3	min_threshold	aon_timer_smoke_min_thold	1.440s	563.540us	1	1	100.00
V3	wkup_count_hi_cdc	aon_timer_wkup_count_cdc_hi	2.400s	3.268ms	1	1	100.00
V3	custom_intr	aon_timer_custom_intr	1.550s	564.498us	1	1	100.00
V3	alternating_on_off	aon_timer_alternating_enable_on_off	4.030s	4.070ms	1	1	100.00
V3	stress_all_with_rand_reset	aon_timer_stress_all_with_rand_reset	1.510s	347.038us	0	1	0.00
V3		TOTAL			5	6	83.33
	Unmapped tests	aon_timer_alert_test	1.670s	387.580us	1	1	100.00
		TOTAL			20	23	86.96

Failure Buckets

• UVM_FATAL (aon_timer_scoreboard.sv:666) scoreboard [scoreboard] Access unexpected addr * has 2 failures:

  • Test aon_timer_stress_all_with_rand_reset has 1 failures.

    • 0.aon_timer_stress_all_with_rand_reset.1
      Line 72, in log /nightly/runs/scratch/master/aon_timer-sim-vcs/0.aon_timer_stress_all_with_rand_reset/latest/run.log

        UVM_FATAL @ 347037831 ps: (aon_timer_scoreboard.sv:666) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Access unexpected addr 0x435bb690
        UVM_INFO @ 347037831 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test aon_timer_tl_errors has 1 failures.

    • 0.aon_timer_tl_errors.1
      Line 70, in log /nightly/runs/scratch/master/aon_timer-sim-vcs/0.aon_timer_tl_errors/latest/run.log

        UVM_FATAL @ 347037831 ps: (aon_timer_scoreboard.sv:666) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Access unexpected addr 0xa4dd5c4
        UVM_INFO @ 347037831 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:297) [aon_timer_common_vseq] Check failed rsp.d_error == exp_err_rsp (* [*] vs * [*]) unexpected error response for addr: * has 1 failures:

  • Test aon_timer_csr_mem_rw_with_rand_reset has 1 failures.

    • 0.aon_timer_csr_mem_rw_with_rand_reset.1
      Line 71, in log /nightly/runs/scratch/master/aon_timer-sim-vcs/0.aon_timer_csr_mem_rw_with_rand_reset/latest/run.log

        UVM_ERROR @ 347079498 ps: (cip_base_vseq.sv:297) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed rsp.d_error == exp_err_rsp (0 [0x0] vs 1 [0x1]) unexpected error response for addr: 0x435bb690
        UVM_INFO @ 347079498 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---