DMA Simulation Results

Tuesday March 18 2025 17:10:07 UTC

GitHub Revision: 6ff667cbce

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	dma_memory_smoke	dma_memory_smoke	6.000s	1.230ms	1	1	100.00
V1	dma_handshake_smoke	dma_handshake_smoke	6.000s	1.284ms	1	1	100.00
V1	dma_generic_smoke	dma_generic_smoke	7.000s	1.573ms	1	1	100.00
V1	csr_hw_reset	dma_csr_hw_reset	4.000s	84.741us	1	1	100.00
V1	csr_rw	dma_csr_rw	4.000s	91.341us	1	1	100.00
V1	csr_bit_bash	dma_csr_bit_bash	9.000s	3.735ms	1	1	100.00
V1	csr_aliasing	dma_csr_aliasing	6.000s	1.373ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	dma_csr_mem_rw_with_rand_reset	4.000s	4.241us	0	1	0.00
V1	regwen_csr_and_corresponding_lockable_csr	dma_csr_rw	4.000s	91.341us	1	1	100.00
		dma_csr_aliasing	6.000s	1.373ms	1	1	100.00
V1		TOTAL			7	8	87.50
V2	dma_memory_region_lock	dma_memory_region_lock	38.000s	15.846ms	1	1	100.00
V2	dma_handshake_stress	dma_handshake_stress	6.333m	207.697ms	1	1	100.00
V2	dma_memory_stress	dma_memory_stress	26.100m	902.889ms	1	1	100.00
V2	dma_generic_stress	dma_generic_stress	4.633m	150.731ms	1	1	100.00
V2	dma_handshake_mem_buffer_overflow	dma_handshake_stress	6.333m	207.697ms	1	1	100.00
V2	dma_abort	dma_abort	12.000s	4.510ms	1	1	100.00
V2	dma_stress_all	dma_stress_all	2.467m	67.501ms	1	1	100.00
V2	intr_test	dma_intr_test	4.000s	50.791us	1	1	100.00
V2	tl_d_oob_addr_access	dma_tl_errors	4.000s	3.841us	0	1	0.00
V2	tl_d_illegal_access	dma_tl_errors	4.000s	3.841us	0	1	0.00
V2	tl_d_outstanding_access	dma_csr_hw_reset	4.000s	84.741us	1	1	100.00
		dma_csr_rw	4.000s	91.341us	1	1	100.00
		dma_csr_aliasing	6.000s	1.373ms	1	1	100.00
		dma_same_csr_outstanding	4.000s	306.741us	1	1	100.00
V2	tl_d_partial_access	dma_csr_hw_reset	4.000s	84.741us	1	1	100.00
		dma_csr_rw	4.000s	91.341us	1	1	100.00
		dma_csr_aliasing	6.000s	1.373ms	1	1	100.00
		dma_same_csr_outstanding	4.000s	306.741us	1	1	100.00
V2		TOTAL			8	9	88.89
V2S	dma_illegal_addr_range	dma_mem_enabled	32.000s	1.776ms	1	1	100.00
		dma_generic_stress	4.633m	150.731ms	1	1	100.00
		dma_handshake_stress	6.333m	207.697ms	1	1	100.00
V2S	tl_intg_err	dma_tl_intg_err	5.000s	547.241us	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	dma_short_transfer	2.033m	76.319ms	1	1	100.00
		dma_longer_transfer	10.000s	2.654ms	1	1	100.00
		TOTAL			19	21	90.48

Failure Buckets

• UVM_ERROR @ *ps: (cip_base_vseq.sv:298) [dma_common_vseq] Check failed rsp.d_error == exp_err_rsp (* [*] vs * [*]) unexpected error response for addr: * has 2 failures:

  • Test dma_tl_errors has 1 failures.

    • 0.dma_tl_errors.1
      Line 85, in log /nightly/runs/scratch/master/dma-sim-xcelium/0.dma_tl_errors/latest/run.log

        UVM_ERROR @    3840573ps: (cip_base_vseq.sv:298) [uvm_test_top.env.virtual_sequencer.dma_common_vseq] Check failed rsp.d_error == exp_err_rsp (0 [0x0] vs 1 [0x1]) unexpected error response for addr: 0x04b47894
        UVM_INFO @    3840573ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test dma_csr_mem_rw_with_rand_reset has 1 failures.

    • 0.dma_csr_mem_rw_with_rand_reset.1
      Line 88, in log /nightly/runs/scratch/master/dma-sim-xcelium/0.dma_csr_mem_rw_with_rand_reset/latest/run.log

        UVM_ERROR @    4240573ps: (cip_base_vseq.sv:298) [uvm_test_top.env.virtual_sequencer.dma_common_vseq] Check failed rsp.d_error == exp_err_rsp (0 [0x0] vs 1 [0x1]) unexpected error response for addr: 0x04b47878
        UVM_INFO @    4240573ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---