KEYMGR_DPE Simulation Results

Tuesday March 18 2025 17:10:07 UTC

GitHub Revision: 6ff667cbce

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	keymgr_dpe_smoke	10.580s	1.652ms	1	1	100.00
V1	csr_hw_reset	keymgr_dpe_csr_hw_reset	1.670s	57.536us	1	1	100.00
V1	csr_rw	keymgr_dpe_csr_rw	1.750s	55.494us	1	1	100.00
V1	csr_bit_bash	keymgr_dpe_csr_bit_bash	6.730s	1.202ms	1	1	100.00
V1	csr_aliasing	keymgr_dpe_csr_aliasing	4.160s	467.039us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	keymgr_dpe_csr_mem_rw_with_rand_reset	1.540s	5.077us	0	1	0.00
V1	regwen_csr_and_corresponding_lockable_csr	keymgr_dpe_csr_rw	1.750s	55.494us	1	1	100.00
		keymgr_dpe_csr_aliasing	4.160s	467.039us	1	1	100.00
V1		TOTAL			5	6	83.33
V2	intr_test	keymgr_dpe_intr_test	1.600s	30.285us	1	1	100.00
V2	alert_test	keymgr_dpe_alert_test	1.430s	38.869us	1	1	100.00
V2	tl_d_oob_addr_access	keymgr_dpe_tl_errors	1.340s	6.910us	0	1	0.00
V2	tl_d_illegal_access	keymgr_dpe_tl_errors	1.340s	6.910us	0	1	0.00
V2	tl_d_outstanding_access	keymgr_dpe_csr_hw_reset	1.670s	57.536us	1	1	100.00
		keymgr_dpe_csr_rw	1.750s	55.494us	1	1	100.00
		keymgr_dpe_csr_aliasing	4.160s	467.039us	1	1	100.00
		keymgr_dpe_same_csr_outstanding	2.310s	165.328us	1	1	100.00
V2	tl_d_partial_access	keymgr_dpe_csr_hw_reset	1.670s	57.536us	1	1	100.00
		keymgr_dpe_csr_rw	1.750s	55.494us	1	1	100.00
		keymgr_dpe_csr_aliasing	4.160s	467.039us	1	1	100.00
		keymgr_dpe_same_csr_outstanding	2.310s	165.328us	1	1	100.00
V2		TOTAL			3	4	75.00
V2S	tl_intg_err	keymgr_dpe_sec_cm	6.560s	1.094ms	1	1	100.00
		keymgr_dpe_tl_intg_err	3.530s	362.621us	1	1	100.00
V2S	shadow_reg_update_error	keymgr_dpe_shadow_reg_errors	2.470s	208.578us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	keymgr_dpe_shadow_reg_errors	2.470s	208.578us	1	1	100.00
V2S	shadow_reg_storage_error	keymgr_dpe_shadow_reg_errors	2.470s	208.578us	1	1	100.00
V2S	shadowed_reset_glitch	keymgr_dpe_shadow_reg_errors	2.470s	208.578us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	keymgr_dpe_shadow_reg_errors_with_csr_rw	4.050s	441.330us	1	1	100.00
V2S	prim_count_check	keymgr_dpe_sec_cm	6.560s	1.094ms	1	1	100.00
V2S	prim_fsm_check	keymgr_dpe_sec_cm	6.560s	1.094ms	1	1	100.00
V2S		TOTAL			4	4	100.00
		TOTAL			12	14	85.71

Failure Buckets

• UVM_FATAL (keymgr_dpe_scoreboard.sv:455) scoreboard [scoreboard] Access unexpected addr * has 1 failures:

  • Test keymgr_dpe_tl_errors has 1 failures.

    • 0.keymgr_dpe_tl_errors.1
      Line 75, in log /nightly/runs/scratch/master/keymgr_dpe-sim-vcs/0.keymgr_dpe_tl_errors/latest/run.log

        UVM_FATAL @   6910110 ps: (keymgr_dpe_scoreboard.sv:455) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Access unexpected addr 0x472fac40
        UVM_INFO @   6910110 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:297) [keymgr_dpe_common_vseq] Check failed rsp.d_error == exp_err_rsp (* [*] vs * [*]) unexpected error response for addr: * has 1 failures:

  • Test keymgr_dpe_csr_mem_rw_with_rand_reset has 1 failures.

    • 0.keymgr_dpe_csr_mem_rw_with_rand_reset.1
      Line 76, in log /nightly/runs/scratch/master/keymgr_dpe-sim-vcs/0.keymgr_dpe_csr_mem_rw_with_rand_reset/latest/run.log

        UVM_ERROR @   5076762 ps: (cip_base_vseq.sv:297) [uvm_test_top.env.virtual_sequencer.keymgr_dpe_common_vseq] Check failed rsp.d_error == exp_err_rsp (0 [0x0] vs 1 [0x1]) unexpected error response for addr: 0x4cc8feb0
        UVM_INFO @   5076762 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---