RV_DM/USE_DMI_INTERFACE Simulation Results

Tuesday March 18 2025 17:10:07 UTC

GitHub Revision: 6ff667cbce

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rv_dm_smoke	1.670s	2.778us	0	1	0.00
V1	jtag_dtm_csr_hw_reset	rv_dm_jtag_dtm_csr_hw_reset	1.400s	2.778us	0	1	0.00
V1	jtag_dtm_csr_rw	rv_dm_jtag_dtm_csr_rw	1.380s	2.778us	0	1	0.00
V1	jtag_dtm_csr_bit_bash	rv_dm_jtag_dtm_csr_bit_bash	1.400s	2.778us	0	1	0.00
V1	jtag_dtm_csr_aliasing	rv_dm_jtag_dtm_csr_aliasing	1.510s	2.778us	0	1	0.00
V1	jtag_dmi_csr_hw_reset	rv_dm_jtag_dmi_csr_hw_reset	1.430s	2.778us	0	1	0.00
V1	jtag_dmi_csr_rw	rv_dm_jtag_dmi_csr_rw	1.510s	2.778us	0	1	0.00
V1	jtag_dmi_csr_bit_bash	rv_dm_jtag_dmi_csr_bit_bash	1.460s	2.778us	0	1	0.00
V1	jtag_dmi_csr_aliasing	rv_dm_jtag_dmi_csr_aliasing	1.390s	2.778us	0	1	0.00
V1	jtag_dmi_cmderr_busy	rv_dm_cmderr_busy	1.560s	2.778us	0	1	0.00
V1	jtag_dmi_cmderr_not_supported	rv_dm_cmderr_not_supported	1.650s	2.778us	0	1	0.00
V1	cmderr_exception	rv_dm_cmderr_exception	1.620s	2.778us	0	1	0.00
V1	mem_tl_access_resuming	rv_dm_mem_tl_access_resuming	1.640s	2.778us	0	1	0.00
V1	mem_tl_access_halted	rv_dm_mem_tl_access_halted	1.620s	2.778us	0	1	0.00
V1	cmderr_halt_resume	rv_dm_cmderr_halt_resume	1.590s	2.778us	0	1	0.00
V1	dataaddr_rw_access	rv_dm_dataaddr_rw_access	1.640s	2.778us	0	1	0.00
V1	halt_resume	rv_dm_halt_resume_whereto	1.670s	2.778us	0	1	0.00
V1	progbuf_busy	rv_dm_cmderr_busy	1.560s	2.778us	0	1	0.00
V1	abstractcmd_status	rv_dm_abstractcmd_status	1.690s	2.778us	0	1	0.00
V1	progbuf_read_write_execute	rv_dm_progbuf_read_write_execute	1.740s	2.778us	0	1	0.00
V1	progbuf_exception	rv_dm_cmderr_exception	1.620s	2.778us	0	1	0.00
V1	rom_read_access	rv_dm_rom_read_access	1.660s	2.778us	0	1	0.00
V1	csr_hw_reset	rv_dm_csr_hw_reset	1.340s	2.778us	0	1	0.00
V1	csr_rw	rv_dm_csr_rw	1.650s	2.778us	0	1	0.00
V1	csr_bit_bash	rv_dm_csr_bit_bash	1.630s	2.778us	0	1	0.00
V1	csr_aliasing	rv_dm_csr_aliasing	1.450s	2.778us	0	1	0.00
V1	csr_mem_rw_with_rand_reset	rv_dm_csr_mem_rw_with_rand_reset	1.570s	2.778us	0	1	0.00
V1	regwen_csr_and_corresponding_lockable_csr	rv_dm_csr_aliasing	1.450s	2.778us	0	1	0.00
		rv_dm_csr_rw	1.650s	2.778us	0	1	0.00
V1	mem_walk	rv_dm_mem_walk	1.570s	2.778us	0	1	0.00
V1	mem_partial_access	rv_dm_mem_partial_access	1.460s	2.778us	0	1	0.00
V1		TOTAL			0	27	0.00
V2	idcode	rv_dm_smoke	1.670s	2.778us	0	1	0.00
V2	jtag_dtm_hard_reset	rv_dm_jtag_dtm_hard_reset	1.620s	2.778us	0	1	0.00
V2	jtag_dtm_idle_hint	rv_dm_jtag_dtm_idle_hint	1.600s	2.778us	0	1	0.00
V2	jtag_dmi_failed_op	rv_dm_dmi_failed_op	1.640s	2.778us	0	1	0.00
V2	jtag_dmi_dm_inactive	rv_dm_jtag_dmi_dm_inactive	1.640s	2.778us	0	1	0.00
V2	sba	rv_dm_sba_tl_access	1.630s	2.778us	0	1	0.00
		rv_dm_delayed_resp_sba_tl_access	1.650s	2.778us	0	1	0.00
V2	bad_sba	rv_dm_bad_sba_tl_access	1.630s	2.778us	0	1	0.00
V2	sba_autoincrement	rv_dm_autoincr_sba_tl_access	1.560s	2.778us	0	1	0.00
V2	jtag_dmi_debug_disabled	rv_dm_jtag_dmi_debug_disabled	1.650s	2.778us	0	1	0.00
V2	sba_debug_disabled	rv_dm_sba_debug_disabled	1.600s	2.020us	0	1	0.00
V2	ndmreset_req	rv_dm_ndmreset_req	1.670s	2.778us	0	1	0.00
V2	hart_unavail	rv_dm_hart_unavail	1.630s	2.778us	0	1	0.00
V2	tap_ctrl_transitions	rv_dm_tap_fsm	1.330s	2.778us	0	1	0.00
		rv_dm_tap_fsm_rand_reset	1.560s	2.778us	0	1	0.00
V2	hartsel_warl	rv_dm_hartsel_warl	1.660s	2.778us	0	1	0.00
V2	stress_all	rv_dm_stress_all	1.680s	2.778us	0	1	0.00
V2	alert_test	rv_dm_alert_test	1.650s	2.778us	0	1	0.00
V2	tl_d_oob_addr_access	rv_dm_tl_errors	1.580s	2.778us	0	1	0.00
V2	tl_d_illegal_access	rv_dm_tl_errors	1.580s	2.778us	0	1	0.00
V2	tl_d_outstanding_access	rv_dm_csr_aliasing	1.450s	2.778us	0	1	0.00
		rv_dm_csr_hw_reset	1.340s	2.778us	0	1	0.00
		rv_dm_csr_rw	1.650s	2.778us	0	1	0.00
		rv_dm_same_csr_outstanding	1.620s	2.778us	0	1	0.00
V2	tl_d_partial_access	rv_dm_csr_aliasing	1.450s	2.778us	0	1	0.00
		rv_dm_csr_hw_reset	1.340s	2.778us	0	1	0.00
		rv_dm_csr_rw	1.650s	2.778us	0	1	0.00
		rv_dm_same_csr_outstanding	1.620s	2.778us	0	1	0.00
V2		TOTAL			0	19	0.00
V2S	tl_intg_err	rv_dm_sec_cm	1.670s	2.778us	0	1	0.00
		rv_dm_tl_intg_err	1.550s	2.778us	0	1	0.00
V2S	sec_cm_bus_integrity	rv_dm_tl_intg_err	1.550s	2.778us	0	1	0.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	rv_dm_sba_debug_disabled	1.600s	2.020us	0	1	0.00
		rv_dm_debug_disabled	1.690s	2.020us	0	1	0.00
V2S	sec_cm_lc_dft_en_intersig_mubi	rv_dm_sba_debug_disabled	1.600s	2.020us	0	1	0.00
		rv_dm_debug_disabled	1.690s	2.020us	0	1	0.00
V2S	sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi	rv_dm_smoke	1.670s	2.778us	0	1	0.00
V2S	sec_cm_dm_en_ctrl_lc_gated	rv_dm_buffered_enable	1.700s	2.020us	0	1	0.00
V2S	sec_cm_sba_tl_lc_gate_fsm_sparse	rv_dm_sparse_lc_gate_fsm	1.710s	2.778us	0	1	0.00
V2S	sec_cm_mem_tl_lc_gate_fsm_sparse	rv_dm_sparse_lc_gate_fsm	1.710s	2.778us	0	1	0.00
V2S	sec_cm_exec_ctrl_mubi	rv_dm_buffered_enable	1.700s	2.020us	0	1	0.00
V2S		TOTAL			0	5	0.00
V3	stress_all_with_rand_reset	rv_dm_stress_all_with_rand_reset	1.690s	2.778us	0	1	0.00
V3		TOTAL			0	1	0.00
	Unmapped tests	rv_dm_scanmode	1.700s	1.847us	0	1	0.00
		TOTAL			0	53	0.00

Failure Buckets

• Offending '(!$isunknown(lc_en_o))' has 53 failures:

  • Test rv_dm_csr_aliasing has 1 failures.

    • 0.rv_dm_csr_aliasing.1
      Line 73, in log /nightly/runs/scratch/master/rv_dm-sim-vcs/0.rv_dm_csr_aliasing/latest/run.log

            Offending '(!$isunknown(lc_en_o))'
        UVM_ERROR @   2778459 ps: (prim_lc_or_hardened.sv:67) [ASSERT FAILED] OutputsKnown_A
        UVM_INFO @   2778459 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test rv_dm_smoke has 1 failures.

    • 0.rv_dm_smoke.1
      Line 73, in log /nightly/runs/scratch/master/rv_dm-sim-vcs/0.rv_dm_smoke/latest/run.log

            Offending '(!$isunknown(lc_en_o))'
        UVM_ERROR @   2778459 ps: (prim_lc_or_hardened.sv:67) [ASSERT FAILED] OutputsKnown_A
        UVM_INFO @   2778459 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test rv_dm_tap_fsm has 1 failures.

    • 0.rv_dm_tap_fsm.1
      Line 73, in log /nightly/runs/scratch/master/rv_dm-sim-vcs/0.rv_dm_tap_fsm/latest/run.log

            Offending '(!$isunknown(lc_en_o))'
        UVM_ERROR @   2778459 ps: (prim_lc_or_hardened.sv:67) [ASSERT FAILED] OutputsKnown_A
        UVM_INFO @   2778459 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test rv_dm_jtag_dtm_csr_hw_reset has 1 failures.

    • 0.rv_dm_jtag_dtm_csr_hw_reset.1
      Line 73, in log /nightly/runs/scratch/master/rv_dm-sim-vcs/0.rv_dm_jtag_dtm_csr_hw_reset/latest/run.log

            Offending '(!$isunknown(lc_en_o))'
        UVM_ERROR @   2778459 ps: (prim_lc_or_hardened.sv:67) [ASSERT FAILED] OutputsKnown_A
        UVM_INFO @   2778459 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test rv_dm_jtag_dtm_csr_rw has 1 failures.

    • 0.rv_dm_jtag_dtm_csr_rw.1
      Line 73, in log /nightly/runs/scratch/master/rv_dm-sim-vcs/0.rv_dm_jtag_dtm_csr_rw/latest/run.log

            Offending '(!$isunknown(lc_en_o))'
        UVM_ERROR @   2778459 ps: (prim_lc_or_hardened.sv:67) [ASSERT FAILED] OutputsKnown_A
        UVM_INFO @   2778459 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • ... and 48 more tests.