HMAC Simulation Results

Wednesday March 19 2025 17:06:27 UTC

GitHub Revision: cf25bf2795

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	hmac_smoke	4.040s	1.189ms	1	1	100.00
V1	csr_hw_reset	hmac_csr_hw_reset	1.440s	77.119us	1	1	100.00
V1	csr_rw	hmac_csr_rw	1.480s	65.036us	1	1	100.00
V1	csr_bit_bash	hmac_csr_bit_bash	4.590s	1.912ms	1	1	100.00
V1	csr_aliasing	hmac_csr_aliasing	3.000s	728.374us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	hmac_csr_mem_rw_with_rand_reset	1.530s	4.160us	0	1	0.00
V1	regwen_csr_and_corresponding_lockable_csr	hmac_csr_rw	1.480s	65.036us	1	1	100.00
		hmac_csr_aliasing	3.000s	728.374us	1	1	100.00
V1		TOTAL			5	6	83.33
V2	long_msg	hmac_long_msg	34.530s	14.003ms	1	1	100.00
V2	back_pressure	hmac_back_pressure	9.470s	945.834us	1	1	100.00
V2	test_vectors	hmac_test_sha256_vectors	6.900s	566.165us	1	1	100.00
		hmac_test_sha384_vectors	14.350s	723.874us	1	1	100.00
		hmac_test_sha512_vectors	14.730s	723.874us	1	1	100.00
		hmac_test_hmac256_vectors	4.810s	546.414us	1	1	100.00
		hmac_test_hmac384_vectors	6.200s	803.208us	1	1	100.00
		hmac_test_hmac512_vectors	6.200s	676.790us	1	1	100.00
V2	burst_wr	hmac_burst_wr	17.840s	7.354ms	1	1	100.00
V2	datapath_stress	hmac_datapath_stress	2.899m	6.680ms	1	1	100.00
V2	error	hmac_error	41.800s	17.177ms	1	1	100.00
V2	wipe_secret	hmac_wipe_secret	19.190s	8.263ms	1	1	100.00
V2	save_and_restore	hmac_smoke	4.040s	1.189ms	1	1	100.00
		hmac_long_msg	34.530s	14.003ms	1	1	100.00
		hmac_back_pressure	9.470s	945.834us	1	1	100.00
		hmac_datapath_stress	2.899m	6.680ms	1	1	100.00
		hmac_burst_wr	17.840s	7.354ms	1	1	100.00
		hmac_stress_all	54.570s	22.796ms	1	1	100.00
V2	fifo_empty_status_interrupt	hmac_smoke	4.040s	1.189ms	1	1	100.00
		hmac_long_msg	34.530s	14.003ms	1	1	100.00
		hmac_back_pressure	9.470s	945.834us	1	1	100.00
		hmac_datapath_stress	2.899m	6.680ms	1	1	100.00
		hmac_wipe_secret	19.190s	8.263ms	1	1	100.00
		hmac_test_sha256_vectors	6.900s	566.165us	1	1	100.00
		hmac_test_sha384_vectors	14.350s	723.874us	1	1	100.00
		hmac_test_sha512_vectors	14.730s	723.874us	1	1	100.00
		hmac_test_hmac256_vectors	4.810s	546.414us	1	1	100.00
		hmac_test_hmac384_vectors	6.200s	803.208us	1	1	100.00
		hmac_test_hmac512_vectors	6.200s	676.790us	1	1	100.00
V2	wide_digest_configurable_key_length	hmac_smoke	4.040s	1.189ms	1	1	100.00
		hmac_long_msg	34.530s	14.003ms	1	1	100.00
		hmac_back_pressure	9.470s	945.834us	1	1	100.00
		hmac_datapath_stress	2.899m	6.680ms	1	1	100.00
		hmac_burst_wr	17.840s	7.354ms	1	1	100.00
		hmac_error	41.800s	17.177ms	1	1	100.00
		hmac_wipe_secret	19.190s	8.263ms	1	1	100.00
		hmac_test_sha256_vectors	6.900s	566.165us	1	1	100.00
		hmac_test_sha384_vectors	14.350s	723.874us	1	1	100.00
		hmac_test_sha512_vectors	14.730s	723.874us	1	1	100.00
		hmac_test_hmac256_vectors	4.810s	546.414us	1	1	100.00
		hmac_test_hmac384_vectors	6.200s	803.208us	1	1	100.00
		hmac_test_hmac512_vectors	6.200s	676.790us	1	1	100.00
		hmac_stress_all	54.570s	22.796ms	1	1	100.00
V2	stress_all	hmac_stress_all	54.570s	22.796ms	1	1	100.00
V2	alert_test	hmac_alert_test	1.280s	39.869us	1	1	100.00
V2	intr_test	hmac_intr_test	1.370s	38.994us	1	1	100.00
V2	tl_d_oob_addr_access	hmac_tl_errors	1.300s	4.827us	0	1	0.00
V2	tl_d_illegal_access	hmac_tl_errors	1.300s	4.827us	0	1	0.00
V2	tl_d_outstanding_access	hmac_csr_hw_reset	1.440s	77.119us	1	1	100.00
		hmac_csr_rw	1.480s	65.036us	1	1	100.00
		hmac_csr_aliasing	3.000s	728.374us	1	1	100.00
		hmac_same_csr_outstanding	1.900s	211.037us	1	1	100.00
V2	tl_d_partial_access	hmac_csr_hw_reset	1.440s	77.119us	1	1	100.00
		hmac_csr_rw	1.480s	65.036us	1	1	100.00
		hmac_csr_aliasing	3.000s	728.374us	1	1	100.00
		hmac_same_csr_outstanding	1.900s	211.037us	1	1	100.00
V2		TOTAL			16	17	94.12
V2S	tl_intg_err	hmac_sec_cm	1.530s	140.244us	1	1	100.00
		hmac_tl_intg_err	2.360s	371.413us	1	1	100.00
V2S	sec_cm_bus_integrity	hmac_tl_intg_err	2.360s	371.413us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	write_config_and_secret_key_during_msg_wr	hmac_smoke	4.040s	1.189ms	1	1	100.00
V3	stress_reset	hmac_stress_reset	1.490s	23.702us	0	1	0.00
V3	stress_all_with_rand_reset	hmac_stress_all_with_rand_reset	1.360s	3.827us	0	1	0.00
V3		TOTAL			0	2	0.00
	Unmapped tests	hmac_directed	1.440s	48.431us	1	1	100.00
		TOTAL			24	28	85.71

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:297) [hmac_common_vseq] Check failed rsp.d_error == exp_err_rsp (* [*] vs * [*]) unexpected error response for addr: * has 2 failures:

  • Test hmac_tl_errors has 1 failures.

    • 0.hmac_tl_errors.1
      Line 70, in log /nightly/runs/scratch/master/hmac-sim-vcs/0.hmac_tl_errors/latest/run.log

        UVM_ERROR @   4826760 ps: (cip_base_vseq.sv:297) [uvm_test_top.env.virtual_sequencer.hmac_common_vseq] Check failed rsp.d_error == exp_err_rsp (0 [0x0] vs 1 [0x1]) unexpected error response for addr: 0x4ea4404c
        UVM_INFO @   4826760 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test hmac_csr_mem_rw_with_rand_reset has 1 failures.

    • 0.hmac_csr_mem_rw_with_rand_reset.1
      Line 71, in log /nightly/runs/scratch/master/hmac-sim-vcs/0.hmac_csr_mem_rw_with_rand_reset/latest/run.log

        UVM_ERROR @   4160088 ps: (cip_base_vseq.sv:297) [uvm_test_top.env.virtual_sequencer.hmac_common_vseq] Check failed rsp.d_error == exp_err_rsp (0 [0x0] vs 1 [0x1]) unexpected error response for addr: 0x4cc959a4
        UVM_INFO @   4160088 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:297) [hmac_stress_reset_vseq] Check failed rsp.d_error == exp_err_rsp (* [*] vs * [*]) unexpected error response for addr: * has 1 failures:

  • Test hmac_stress_reset has 1 failures.

    • 0.hmac_stress_reset.1
      Line 90, in log /nightly/runs/scratch/master/hmac-sim-vcs/0.hmac_stress_reset/latest/run.log

        UVM_ERROR @  23701911 ps: (cip_base_vseq.sv:297) [uvm_test_top.env.virtual_sequencer.hmac_stress_reset_vseq] Check failed rsp.d_error == exp_err_rsp (0 [0x0] vs 1 [0x1]) unexpected error response for addr: 0x4ea440cc
        UVM_INFO @  23701911 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (hmac_scoreboard.sv:134) scoreboard [scoreboard] Access unexpected addr * has 1 failures:

  • Test hmac_stress_all_with_rand_reset has 1 failures.

    • 0.hmac_stress_all_with_rand_reset.1
      Line 71, in log /nightly/runs/scratch/master/hmac-sim-vcs/0.hmac_stress_all_with_rand_reset/latest/run.log

        UVM_FATAL @   3826752 ps: (hmac_scoreboard.sv:134) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Access unexpected addr 0x4cc959a4
        UVM_INFO @   3826752 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---