CHIP Simulation Results

Thursday March 20 2025 17:02:06 UTC

GitHub Revision: `9e459976c7`

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	chip_sw_uart_tx_rx	chip_sw_uart_tx_rx	20.030s		0	1	0.00
V1	chip_sw_uart_rx_overflow	chip_sw_uart_tx_rx	20.030s		0	1	0.00
V1	chip_sw_uart_rand_baudrate	chip_sw_uart_rand_baudrate	11.046s		0	1	0.00
V1	chip_sw_uart_tx_rx_alt_clk_freq	chip_sw_uart_tx_rx_alt_clk_freq	11.055s		0	1	0.00
		chip_sw_uart_tx_rx_alt_clk_freq_low_speed	11.053s		0	1	0.00
V1	chip_sw_gpio_out	chip_sw_gpio	5.798m	6.408ms	1	1	100.00
V1	chip_sw_gpio_in	chip_sw_gpio	5.798m	6.408ms	1	1	100.00
V1	chip_sw_gpio_irq	chip_sw_gpio	5.798m	6.408ms	1	1	100.00
V1	chip_sw_example_tests	chip_sw_example_rom	34.039s		0	1	0.00
		chip_sw_example_manufacturer	32.031s		0	1	0.00
		chip_sw_example_concurrency	10.035s		0	1	0.00
		chip_sw_uart_smoketest_signed	17.081s		0	1	0.00
V1	csr_hw_reset	chip_csr_hw_reset	4.149m	6.400ms	0	1	0.00
V1	csr_rw	chip_csr_rw	2.608m	3.710ms	0	1	0.00
V1	csr_bit_bash	chip_csr_bit_bash	5.106m	5.400ms	1	1	100.00
V1	csr_aliasing	chip_csr_aliasing	25.290m	15.715ms	0	1	0.00
V1	csr_mem_rw_with_rand_reset	chip_csr_mem_rw_with_rand_reset	2.645m	3.702ms	0	1	0.00
V1	regwen_csr_and_corresponding_lockable_csr	chip_csr_aliasing	25.290m	15.715ms	0	1	0.00
		chip_csr_rw	2.608m	3.710ms	0	1	0.00
V1	xbar_smoke	xbar_smoke	14.750s	49.909us	1	1	100.00
V1		TOTAL			3	15	20.00
V2	chip_sw_spi_device_flash_mode	chip_sw_uart_tx_rx_bootstrap	14.028s		0	1	0.00
V2	chip_sw_spi_device_pass_through	chip_sw_spi_device_pass_through	6.817m	7.971ms	1	1	100.00
V2	chip_sw_spi_device_pass_through_collision	chip_sw_spi_device_pass_through_collision	3.844m	4.572ms	0	1	0.00
V2	chip_sw_spi_device_tpm	chip_sw_spi_device_tpm	10.045s		0	1	0.00
V2	chip_sw_spi_host_tx_rx	chip_sw_spi_host_tx_rx	10.042s		0	1	0.00
V2	chip_sw_i2c_host_tx_rx	chip_sw_i2c_host_tx_rx	11.049s		0	1	0.00
V2	chip_sw_i2c_device_tx_rx	chip_sw_i2c_device_tx_rx	10.048s		0	1	0.00
V2	chip_pin_mux	chip_padctrl_attributes	3.150s		0	1	0.00
V2	chip_padctrl_attributes	chip_padctrl_attributes	3.150s		0	1	0.00
V2	chip_sw_sleep_pin_wake	chip_sw_sleep_pin_wake	1.819m		0	1	0.00
V2	chip_sw_sleep_pin_retention	chip_sw_sleep_pin_retention	27.042s		0	1	0.00
V2	chip_sw_data_integrity	chip_sw_data_integrity_escalation	1.902m		0	1	0.00
V2	chip_sw_instruction_integrity	chip_sw_data_integrity_escalation	1.902m		0	1	0.00
V2	chip_jtag_csr_rw	chip_jtag_csr_rw	2.555m	3.683ms	0	1	0.00
V2	chip_jtag_mem_access	chip_jtag_mem_access	2.653m	3.683ms	0	1	0.00
V2	chip_rv_dm_ndm_reset_req	chip_rv_dm_ndm_reset_req	11.049s		0	1	0.00
V2	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	10.046s		0	1	0.00
V2	chip_rv_dm_access_after_wakeup	chip_sw_rv_dm_access_after_wakeup	10.042s		0	1	0.00
V2	chip_rv_dm_lc_disabled	chip_rv_dm_lc_disabled	10.932m	17.314ms	1	1	100.00
V2	chip_sw_timer	chip_sw_rv_timer_irq	5.570m	6.196ms	1	1	100.00
V2	chip_sw_aon_timer_wakeup_irq	chip_sw_aon_timer_irq	11.035s		0	1	0.00
V2	chip_sw_aon_timer_wdog_bark_irq	chip_sw_aon_timer_irq	11.035s		0	1	0.00
V2	chip_sw_aon_timer_wdog_lc_escalate	chip_sw_aon_timer_wdog_lc_escalate	11.062s		0	1	0.00
V2	chip_sw_aon_timer_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	10.062s		0	1	0.00
V2	chip_sw_aon_timer_sleep_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	10.062s		0	1	0.00
V2	chip_sw_aon_timer_sleep_wdog_sleep_pause	chip_sw_aon_timer_sleep_wdog_sleep_pause	11.045s		0	1	0.00
V2	chip_sw_plic_all_irqs	chip_plic_all_irqs	11.035s		0	1	0.00
V2	chip_sw_plic_sw_irq	chip_sw_plic_sw_irq	3.233m	4.161ms	1	1	100.00
V2	chip_sw_clkmgr_idle_trans	chip_sw_otbn_randomness	3.881m	4.858ms	1	1	100.00
		chip_sw_aes_idle	3.458m	4.181ms	1	1	100.00
		chip_sw_hmac_enc_idle	11.019s		0	1	0.00
		chip_sw_kmac_idle	3.165m	4.134ms	1	1	100.00
V2	chip_sw_clkmgr_off_trans	chip_sw_clkmgr_off_aes_trans	11.024s		0	1	0.00
		chip_sw_clkmgr_off_hmac_trans	11.022s		0	1	0.00
		chip_sw_clkmgr_off_kmac_trans	11.024s		0	1	0.00
		chip_sw_clkmgr_off_otbn_trans	11.019s		0	1	0.00
V2	chip_sw_clkmgr_div	chip_sw_clkmgr_external_clk_src_for_lc	11.019s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	11.029s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	11.040s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	10.023s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	11.036s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	10.056s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	10.058s		0	1	0.00
V2	chip_sw_clkmgr_external_clk_src_for_lc	chip_sw_clkmgr_external_clk_src_for_lc	11.019s		0	1	0.00
V2	chip_sw_clkmgr_external_clk_src_for_sw	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	11.029s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	11.040s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	10.023s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	11.036s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	10.056s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	10.058s		0	1	0.00
V2	chip_sw_clkmgr_jitter	chip_sw_otbn_ecdsa_op_irq_jitter_en	11.049s		0	1	0.00
		chip_sw_aes_enc_jitter_en	42.970s	10.200us	0	1	0.00
		chip_sw_edn_entropy_reqs_jitter	11.030s		0	1	0.00
		chip_sw_hmac_enc_jitter_en	43.030s	10.200us	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	43.550s	10.200us	0	1	0.00
		chip_sw_kmac_mode_kmac_jitter_en	43.250s	10.200us	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	11.031s		0	1	0.00
		chip_sw_clkmgr_jitter	3.064m	4.072ms	1	1	100.00
V2	chip_sw_clkmgr_extended_range	chip_sw_clkmgr_jitter_reduced_freq	3.049m	4.072ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq	11.025s		0	1	0.00
		chip_sw_aes_enc_jitter_en_reduced_freq	43.260s	10.200us	0	1	0.00
		chip_sw_hmac_enc_jitter_en_reduced_freq	42.770s	10.200us	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en_reduced_freq	42.390s	10.200us	0	1	0.00
		chip_sw_kmac_mode_kmac_jitter_en_reduced_freq	42.830s	10.200us	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq	10.044s		0	1	0.00
		chip_sw_csrng_edn_concurrency_reduced_freq	10.036s		0	1	0.00
V2	chip_sw_clkmgr_deep_sleep_frequency	chip_sw_ast_clk_outputs	11.047s		0	1	0.00
V2	chip_sw_clkmgr_sleep_frequency	chip_sw_clkmgr_sleep_frequency	11.053s		0	1	0.00
V2	chip_sw_clkmgr_reset_frequency	chip_sw_clkmgr_reset_frequency	12.063s		0	1	0.00
V2	chip_sw_clkmgr_escalation_reset	chip_sw_all_escalation_resets	15.539m	16.581ms	0	1	0.00
V2	chip_sw_pwrmgr_external_full_reset	chip_sw_pwrmgr_full_aon_reset	11.010s		0	1	0.00
V2	chip_sw_pwrmgr_sleep_all_reset_reqs	chip_sw_aon_timer_wdog_bite_reset	10.062s		0	1	0.00
V2	chip_sw_pwrmgr_wdog_reset	chip_sw_pwrmgr_wdog_reset	11.067s		0	1	0.00
V2	chip_sw_pwrmgr_aon_power_glitch_reset	chip_sw_pwrmgr_full_aon_reset	11.010s		0	1	0.00
V2	chip_sw_pwrmgr_main_power_glitch_reset	chip_sw_pwrmgr_main_power_glitch_reset	11.009s		0	1	0.00
V2	chip_sw_pwrmgr_random_sleep_power_glitch_reset	chip_sw_pwrmgr_random_sleep_power_glitch_reset	10.009s		0	1	0.00
V2	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	11.010s		0	1	0.00
V2	chip_sw_pwrmgr_sleep_power_glitch_reset	chip_sw_pwrmgr_sleep_power_glitch_reset	11.009s		0	1	0.00
V2	chip_sw_pwrmgr_sleep_disabled	chip_sw_pwrmgr_sleep_disabled	10.009s		0	1	0.00
V2	chip_sw_pwrmgr_escalation_reset	chip_sw_all_escalation_resets	15.539m	16.581ms	0	1	0.00
V2	chip_sw_rstmgr_sys_reset_info	chip_rv_dm_ndm_reset_req	11.049s		0	1	0.00
V2	chip_sw_rstmgr_cpu_info	chip_sw_rstmgr_cpu_info	13.811m	20.027ms	0	1	0.00
V2	chip_sw_rstmgr_sw_req_reset	chip_sw_rstmgr_sw_req	8.686m	12.027ms	0	1	0.00
V2	chip_sw_rstmgr_alert_info	chip_sw_rstmgr_alert_info	5.704m	7.085ms	0	1	0.00
V2	chip_sw_rstmgr_sw_rst	chip_sw_rstmgr_sw_rst	3.039m	4.116ms	1	1	100.00
V2	chip_sw_rstmgr_escalation_reset	chip_sw_all_escalation_resets	15.539m	16.581ms	0	1	0.00
V2	chip_sw_alert_handler_alerts	chip_sw_alert_test	12.059s		0	1	0.00
V2	chip_sw_alert_handler_escalations	chip_sw_alert_handler_escalation	12.029s		0	1	0.00
V2	chip_sw_all_escalation_resets	chip_sw_all_escalation_resets	15.539m	16.581ms	0	1	0.00
V2	chip_sw_alert_handler_irqs	chip_plic_all_irqs	11.035s		0	1	0.00
V2	chip_sw_alert_handler_entropy	chip_sw_alert_handler_entropy	11.046s		0	1	0.00
V2	chip_sw_alert_handler_crashdump	chip_sw_rstmgr_alert_info	5.704m	7.085ms	0	1	0.00
V2	chip_sw_alert_handler_ping_timeout	chip_sw_alert_handler_ping_timeout	14.034s		0	1	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_alerts	chip_sw_alert_handler_lpg_sleep_mode_alerts	11.041s		0	1	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_pings	chip_sw_alert_handler_lpg_sleep_mode_pings	11.041s		0	1	0.00
V2	chip_sw_alert_handler_lpg_clock_off	chip_sw_alert_handler_lpg_clkoff	11.040s		0	1	0.00
V2	chip_sw_alert_handler_lpg_reset_toggle	chip_sw_alert_handler_lpg_reset_toggle	11.039s		0	1	0.00
V2	chip_sw_alert_handler_reverse_ping_in_deep_sleep	chip_sw_alert_handler_reverse_ping_in_deep_sleep	17.042s		0	1	0.00
V2	chip_sw_lc_ctrl_alert_handler_escalation	chip_sw_alert_handler_escalation	12.029s		0	1	0.00
V2	chip_sw_lc_ctrl_jtag_access	chip_sw_lc_ctrl_transition	11.027s		0	1	0.00
V2	chip_sw_lc_ctrl_otp_hw_cfg	chip_sw_lc_ctrl_otp_hw_cfg	11.034s		0	1	0.00
V2	chip_sw_lc_ctrl_init	chip_sw_lc_ctrl_transition	11.027s		0	1	0.00
V2	chip_sw_lc_ctrl_transitions	chip_sw_lc_ctrl_transition	11.027s		0	1	0.00
V2	chip_sw_lc_ctrl_kmac_req	chip_sw_lc_ctrl_transition	11.027s		0	1	0.00
V2	chip_sw_lc_ctrl_key_div	chip_sw_keymgr_dpe_key_derivation_prod	5.558m	6.999ms	0	1	0.00
V2	chip_sw_lc_ctrl_broadcast	chip_sw_otp_ctrl_lc_signals_test_unlocked0	11.030s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_dev	10.036s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_prod	10.035s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_rma	10.031s		0	1	0.00
		chip_sw_lc_ctrl_transition	11.027s		0	1	0.00
		chip_sw_keymgr_dpe_key_derivation	5.533m	6.999ms	0	1	0.00
		chip_sw_rom_ctrl_integrity_check	8.024m	11.760ms	1	1	100.00
		chip_sw_sram_ctrl_execution_main	11.027s		0	1	0.00
		chip_prim_tl_access	9.079m	13.660ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_lc	11.019s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	11.029s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	11.040s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	10.023s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	11.036s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	10.056s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	10.058s		0	1	0.00
		chip_rv_dm_lc_disabled	10.932m	17.314ms	1	1	100.00
V2	chip_sw_aes_enc	chip_sw_aes_enc	3.690m	4.362ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	42.970s	10.200us	0	1	0.00
V2	chip_sw_aes_entropy	chip_sw_aes_entropy	10.068m	15.027ms	0	1	0.00
V2	chip_sw_aes_idle	chip_sw_aes_idle	3.458m	4.181ms	1	1	100.00
V2	chip_sw_hmac_enc	chip_sw_hmac_enc	3.403m	4.363ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	43.030s	10.200us	0	1	0.00
V2	chip_sw_hmac_idle	chip_sw_hmac_enc_idle	11.019s		0	1	0.00
V2	chip_sw_kmac_enc	chip_sw_kmac_mode_cshake	8.570m	12.027ms	0	1	0.00
		chip_sw_kmac_mode_kmac	8.990m	12.027ms	0	1	0.00
		chip_sw_kmac_mode_kmac_jitter_en	43.250s	10.200us	0	1	0.00
V2	chip_sw_kmac_app_keymgr	chip_sw_keymgr_dpe_key_derivation	5.533m	6.999ms	0	1	0.00
V2	chip_sw_kmac_app_lc	chip_sw_lc_ctrl_transition	11.027s		0	1	0.00
V2	chip_sw_kmac_app_rom	chip_sw_kmac_app_rom	35.380s	10.200us	0	1	0.00
V2	chip_sw_kmac_entropy	chip_sw_kmac_entropy	12.030s		0	1	0.00
V2	chip_sw_kmac_idle	chip_sw_kmac_idle	3.165m	4.134ms	1	1	100.00
V2	chip_sw_entropy_src_csrng	chip_sw_entropy_src_csrng	11.027s		0	1	0.00
V2	chip_sw_csrng_edn_cmd	chip_sw_entropy_src_csrng	11.027s		0	1	0.00
V2	chip_sw_csrng_fuse_en_sw_app_read	chip_sw_csrng_fuse_en_sw_app_read_test	11.030s		0	1	0.00
V2	chip_sw_csrng_known_answer_tests	chip_sw_csrng_kat_test	3.230m	4.199ms	1	1	100.00
V2	chip_sw_edn_entropy_reqs	chip_sw_csrng_edn_concurrency	11.038s		0	1	0.00
		chip_sw_edn_entropy_reqs	11.032s		0	1	0.00
V2	chip_sw_keymgr_dpe_key_derivation	chip_sw_keymgr_dpe_key_derivation	5.533m	6.999ms	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	43.550s	10.200us	0	1	0.00
V2	chip_sw_otbn_op	chip_sw_otbn_ecdsa_op_irq	13.046s		0	1	0.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	11.049s		0	1	0.00
V2	chip_sw_otbn_rnd_entropy	chip_sw_otbn_randomness	3.881m	4.858ms	1	1	100.00
V2	chip_sw_otbn_urnd_entropy	chip_sw_otbn_randomness	3.881m	4.858ms	1	1	100.00
V2	chip_sw_otbn_idle	chip_sw_otbn_randomness	3.881m	4.858ms	1	1	100.00
V2	chip_sw_otbn_mem_scramble	chip_sw_otbn_mem_scramble	11.101s		0	1	0.00
V2	chip_sw_rom_access	chip_sw_rom_ctrl_integrity_check	8.024m	11.760ms	1	1	100.00
V2	chip_sw_rom_ctrl_integrity_check	chip_sw_rom_ctrl_integrity_check	8.024m	11.760ms	1	1	100.00
V2	chip_sw_sram_scrambled_access	chip_sw_sram_ctrl_scrambled_access	11.024s		0	1	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	11.031s		0	1	0.00
V2	chip_sw_sram_execution	chip_sw_sram_ctrl_execution_main	11.027s		0	1	0.00
V2	chip_sw_sram_lc_escalation	chip_sw_all_escalation_resets	15.539m	16.581ms	0	1	0.00
		chip_sw_data_integrity_escalation	1.902m		0	1	0.00
V2	chip_otp_ctrl_init	chip_sw_lc_ctrl_transition	11.027s		0	1	0.00
V2	chip_sw_otp_ctrl_keys	chip_sw_otbn_mem_scramble	11.101s		0	1	0.00
		chip_sw_keymgr_dpe_key_derivation	5.533m	6.999ms	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access	11.024s		0	1	0.00
		chip_sw_rv_core_ibex_icache_invalidate	12.038s		0	1	0.00
V2	chip_sw_otp_ctrl_entropy	chip_sw_otbn_mem_scramble	11.101s		0	1	0.00
		chip_sw_keymgr_dpe_key_derivation	5.533m	6.999ms	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access	11.024s		0	1	0.00
		chip_sw_rv_core_ibex_icache_invalidate	12.038s		0	1	0.00
V2	chip_sw_otp_ctrl_program	chip_sw_lc_ctrl_transition	11.027s		0	1	0.00
V2	chip_sw_otp_ctrl_program_error	chip_sw_lc_ctrl_program_error	11.046s		0	1	0.00
V2	chip_sw_otp_ctrl_hw_cfg	chip_sw_lc_ctrl_otp_hw_cfg	11.034s		0	1	0.00
V2	chip_sw_otp_ctrl_lc_signals	chip_sw_otp_ctrl_lc_signals_test_unlocked0	11.030s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_dev	10.036s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_prod	10.035s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_rma	10.031s		0	1	0.00
		chip_sw_lc_ctrl_transition	11.027s		0	1	0.00
		chip_prim_tl_access	9.079m	13.660ms	1	1	100.00
V2	chip_sw_otp_prim_tl_access	chip_prim_tl_access	9.079m	13.660ms	1	1	100.00
V2	chip_sw_otp_ctrl_nvm_cnt	chip_sw_otp_ctrl_nvm_cnt	11.031s		0	1	0.00
V2	chip_sw_otp_ctrl_sw_parts	chip_sw_otp_ctrl_sw_parts	11.029s		0	1	0.00
V2	chip_sw_ast_clk_outputs	chip_sw_ast_clk_outputs	11.047s		0	1	0.00
V2	chip_sw_ast_sys_clk_jitter	chip_sw_otbn_ecdsa_op_irq_jitter_en	11.049s		0	1	0.00
		chip_sw_aes_enc_jitter_en	42.970s	10.200us	0	1	0.00
		chip_sw_edn_entropy_reqs_jitter	11.030s		0	1	0.00
		chip_sw_hmac_enc_jitter_en	43.030s	10.200us	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	43.550s	10.200us	0	1	0.00
		chip_sw_kmac_mode_kmac_jitter_en	43.250s	10.200us	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	11.031s		0	1	0.00
		chip_sw_clkmgr_jitter	3.064m	4.072ms	1	1	100.00
V2	chip_sw_ast_alerts	chip_sw_sensor_ctrl_alert	11.024s		0	1	0.00
V2	chip_sw_sensor_ctrl_ast_alerts	chip_sw_sensor_ctrl_alert	11.024s		0	1	0.00
		chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	11.047s		0	1	0.00
V2	chip_sw_sensor_ctrl_ast_status	chip_sw_sensor_ctrl_status	11.050s		0	1	0.00
V2	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	11.047s		0	1	0.00
V2	chip_sw_soc_proxy_external_reset_requests	chip_sw_soc_proxy_smoketest	11.067s		0	1	0.00
V2	chip_sw_soc_proxy_external_irqs	chip_sw_soc_proxy_smoketest	11.067s		0	1	0.00
V2	chip_sw_soc_proxy_external_alerts	chip_sw_soc_proxy_external_alerts	11.037s		0	1	0.00
V2	chip_sw_soc_proxy_external_wakeup_requests	chip_sw_soc_proxy_external_wakeup	11.032s		0	1	0.00
V2	chip_sw_soc_proxy_gpios	chip_sw_soc_proxy_gpios	11.034s		0	1	0.00
V2	chip_sw_nmi_irq	chip_sw_rv_core_ibex_nmi_irq	5.639m	6.408ms	0	1	0.00
V2	chip_sw_rv_core_ibex_rnd	chip_sw_rv_core_ibex_rnd	3.503m	4.469ms	1	1	100.00
V2	chip_sw_rv_core_ibex_address_translation	chip_sw_rv_core_ibex_address_translation	3.810m	4.519ms	1	1	100.00
V2	chip_sw_rv_core_ibex_icache_scrambled_access	chip_sw_rv_core_ibex_icache_invalidate	12.038s		0	1	0.00
V2	chip_sw_rv_core_ibex_fault_dump	chip_sw_rstmgr_cpu_info	13.811m	20.027ms	0	1	0.00
V2	chip_sw_rv_core_ibex_double_fault	chip_sw_rstmgr_cpu_info	13.811m	20.027ms	0	1	0.00
V2	chip_sw_smoketest	chip_sw_aes_smoketest	15.084s		0	1	0.00
		chip_sw_aon_timer_smoketest	11.071s		0	1	0.00
		chip_sw_clkmgr_smoketest	11.069s		0	1	0.00
		chip_sw_csrng_smoketest	11.067s		0	1	0.00
		chip_sw_gpio_smoketest	2.957m	4.382ms	1	1	100.00
		chip_sw_hmac_smoketest	21.106s		0	1	0.00
		chip_sw_kmac_smoketest	19.090s		0	1	0.00
		chip_sw_otbn_smoketest	21.091s		0	1	0.00
		chip_sw_otp_ctrl_smoketest	14.088s		0	1	0.00
		chip_sw_rv_plic_smoketest	13.073s		0	1	0.00
		chip_sw_rv_timer_smoketest	3.984m	6.196ms	1	1	100.00
		chip_sw_rstmgr_smoketest	17.109s		0	1	0.00
		chip_sw_sram_ctrl_smoketest	14.070s		0	1	0.00
		chip_sw_uart_smoketest	2.849m	4.348ms	1	1	100.00
V2	chip_sw_rom_functests	rom_keymgr_functest	14.075s		0	1	0.00
V2	chip_sw_signed	chip_sw_uart_smoketest_signed	17.081s		0	1	0.00
V2	chip_sw_boot	chip_sw_uart_tx_rx_bootstrap	14.028s		0	1	0.00
V2	chip_sw_secure_boot	base_rom_e2e_smoke	12.015s		0	1	0.00
V2	chip_lc_scrap	chip_sw_lc_ctrl_rma_to_scrap	2.913m	4.656ms	1	1	100.00
		chip_sw_lc_ctrl_raw_to_scrap	3.217m	4.656ms	1	1	100.00
		chip_sw_lc_ctrl_test_locked0_to_scrap	3.163m	4.656ms	1	1	100.00
		chip_sw_lc_ctrl_rand_to_scrap	3.346m	4.656ms	1	1	100.00
V2	chip_lc_test_locked	chip_sw_lc_walkthrough_testunlocks	10.022s		0	1	0.00
		chip_rv_dm_lc_disabled	10.932m	17.314ms	1	1	100.00
V2	chip_sw_lc_walkthrough	chip_sw_lc_walkthrough_dev	11.012s		0	1	0.00
		chip_sw_lc_walkthrough_prod	11.025s		0	1	0.00
		chip_sw_lc_walkthrough_prodend	10.010s		0	1	0.00
		chip_sw_lc_walkthrough_rma	10.018s		0	1	0.00
		chip_sw_lc_walkthrough_testunlocks	10.022s		0	1	0.00
V2	chip_sw_lc_ctrl_volatile_raw_unlock	chip_sw_lc_ctrl_volatile_raw_unlock	10.022s		0	1	0.00
		chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	10.020s		0	1	0.00
		rom_volatile_raw_unlock	10.077s		0	1	0.00
V2	chip_sw_rom_raw_unlock	rom_raw_unlock	10.074s		0	1	0.00
V2	chip_sw_exit_test_unlocked_bootstrap	chip_sw_exit_test_unlocked_bootstrap	11.047s		0	1	0.00
V2	chip_sw_inject_scramble_seed	chip_sw_inject_scramble_seed	12.045s		0	1	0.00
V2	tl_d_oob_addr_access	chip_tl_errors	2.699m	3.703ms	0	1	0.00
V2	tl_d_illegal_access	chip_tl_errors	2.699m	3.703ms	0	1	0.00
V2	tl_d_outstanding_access	chip_csr_aliasing	25.290m	15.715ms	0	1	0.00
		chip_same_csr_outstanding	4.404m	5.130ms	0	1	0.00
		chip_csr_hw_reset	4.149m	6.400ms	0	1	0.00
		chip_csr_rw	2.608m	3.710ms	0	1	0.00
V2	tl_d_partial_access	chip_csr_aliasing	25.290m	15.715ms	0	1	0.00
		chip_same_csr_outstanding	4.404m	5.130ms	0	1	0.00
		chip_csr_hw_reset	4.149m	6.400ms	0	1	0.00
		chip_csr_rw	2.608m	3.710ms	0	1	0.00
V2	xbar_base_random_sequence	xbar_random	2.960m	510.675us	1	1	100.00
V2	xbar_random_delay	xbar_smoke_zero_delays	7.910s	10.734us	1	1	100.00
		xbar_smoke_large_delays	3.636m	2.073ms	1	1	100.00
		xbar_smoke_slow_rsp	4.377m	1.822ms	1	1	100.00
		xbar_random_zero_delays	1.221m	74.809us	1	1	100.00
		xbar_random_large_delays	22.670m	12.543ms	1	1	100.00
		xbar_random_slow_rsp	36.057m	14.519ms	1	1	100.00
V2	xbar_unmapped_address	xbar_unmapped_addr	1.661m	221.078us	1	1	100.00
		xbar_error_and_unmapped_addr	1.630m	221.797us	1	1	100.00
V2	xbar_error_cases	xbar_error_random	2.848m	510.675us	1	1	100.00
		xbar_error_and_unmapped_addr	1.630m	221.797us	1	1	100.00
V2	xbar_all_access_same_device	xbar_access_same_device	4.685m	835.777us	1	1	100.00
		xbar_access_same_device_slow_rsp	59.362m	24.061ms	1	1	100.00
V2	xbar_all_hosts_use_same_source_id	xbar_same_source	59.460s	199.661us	1	1	100.00
V2	xbar_stress_all	xbar_stress_all	10.139m	1.684ms	1	1	100.00
		xbar_stress_all_with_error	9.206m	1.684ms	1	1	100.00
V2	xbar_stress_with_reset	xbar_stress_all_with_rand_reset	28.674m	2.777ms	1	1	100.00
		xbar_stress_all_with_reset_error	23.426m	2.777ms	1	1	100.00
V2	rom_e2e_smoke	rom_e2e_smoke	11.015s		0	1	0.00
V2	rom_e2e_shutdown_output	rom_e2e_shutdown_output	10.016s		0	1	0.00
V2	rom_e2e_shutdown_exception_c	rom_e2e_shutdown_exception_c	11.016s		0	1	0.00
V2	rom_e2e_boot_policy_valid	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	10.034s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_dev	10.044s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod	11.043s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod_end	10.040s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_rma	11.040s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	11.036s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_dev	10.033s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod	11.031s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	11.034s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_rma	10.039s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	10.044s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_dev	10.044s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod	10.044s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	10.043s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_rma	10.041s		0	1	0.00
V2	rom_e2e_sigverify_always	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	10.043s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_dev	11.052s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod	14.119s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod_end	12.112s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_rma	10.129s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	11.133s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_dev	11.134s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod	11.131s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	10.116s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_rma	10.118s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	10.132s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_dev	10.126s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod	15.129s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	14.118s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_rma	14.115s		0	1	0.00
V2	rom_e2e_asm_init	rom_e2e_asm_init_test_unlocked0	12.108s		0	1	0.00
		rom_e2e_asm_init_dev	11.101s		0	1	0.00
		rom_e2e_asm_init_prod	11.116s		0	1	0.00
		rom_e2e_asm_init_prod_end	11.113s		0	1	0.00
		rom_e2e_asm_init_rma	11.111s		0	1	0.00
V2	rom_e2e_keymgr_init	rom_e2e_keymgr_init_rom_ext_meas	10.064s		0	1	0.00
		rom_e2e_keymgr_init_rom_ext_no_meas	10.077s		0	1	0.00
		rom_e2e_keymgr_init_rom_ext_invalid_meas	10.075s		0	1	0.00
V2	rom_e2e_static_critical	rom_e2e_static_critical	10.067s		0	1	0.00
V2		TOTAL			41	211	19.43
V2S	chip_sw_aes_masking_off	chip_sw_aes_masking_off	16.091s		0	1	0.00
V2S	chip_sw_rv_core_ibex_lockstep_glitch	chip_sw_rv_core_ibex_lockstep_glitch	3.002m	4.072ms	1	1	100.00
V2S		TOTAL			1	2	50.00
V3	chip_rv_dm_perform_debug	rom_e2e_jtag_debug_test_unlocked0	11.077s		0	1	0.00
		rom_e2e_jtag_debug_dev	10.075s		0	1	0.00
		rom_e2e_jtag_debug_rma	11.079s		0	1	0.00
V3	chip_sw_rv_dm_access_after_hw_reset	chip_sw_rv_dm_access_after_escalation_reset	10.042s		0	1	0.00
V3	chip_sw_plic_alerts	chip_sw_all_escalation_resets	15.539m	16.581ms	0	1	0.00
V3	chip_sw_otp_ctrl_vendor_test_csr_access	chip_sw_otp_ctrl_vendor_test_csr_access	10.027s		0	1	0.00
V3	chip_sw_otp_ctrl_escalation	chip_sw_otp_ctrl_escalation	12.585m	16.583ms	0	1	0.00
V3	chip_sw_coremark	chip_sw_coremark	11.041s		0	1	0.00
V3	chip_sw_power_max_load	chip_sw_power_virus	10.032s		0	1	0.00
V3	rom_e2e_debug	rom_e2e_jtag_debug_test_unlocked0	11.077s		0	1	0.00
		rom_e2e_jtag_debug_dev	10.075s		0	1	0.00
		rom_e2e_jtag_debug_rma	11.079s		0	1	0.00
V3	rom_e2e_jtag_inject	rom_e2e_jtag_inject_test_unlocked0	10.075s		0	1	0.00
		rom_e2e_jtag_inject_dev	10.073s		0	1	0.00
		rom_e2e_jtag_inject_rma	10.069s		0	1	0.00
V3	rom_e2e_self_hash	rom_e2e_self_hash	35.208s		0	1	0.00
V3		TOTAL			0	12	0.00
	Unmapped tests	chip_sw_rstmgr_rst_cnsty_escalation	14.356m	16.583ms	0	1	0.00
		chip_sw_dma_inline_hashing	3.744m	5.037ms	1	1	100.00
		chip_sw_dma_abort	3.489m	4.499ms	0	1	0.00
		rom_e2e_sigverify_mod_exp_test_unlocked0_otbn	10.072s		0	1	0.00
		rom_e2e_sigverify_mod_exp_test_unlocked0_sw	10.083s		0	1	0.00
		rom_e2e_sigverify_mod_exp_dev_otbn	10.086s		0	1	0.00
		rom_e2e_sigverify_mod_exp_dev_sw	10.085s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_otbn	10.075s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_sw	10.073s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_end_otbn	10.070s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_end_sw	10.067s		0	1	0.00
		rom_e2e_sigverify_mod_exp_rma_otbn	10.065s		0	1	0.00
		rom_e2e_sigverify_mod_exp_rma_sw	10.079s		0	1	0.00
		chip_sw_mbx_smoketest	3.417m	4.719ms	1	1	100.00
		TOTAL			47	254	18.50

Failure Buckets

Job returned non-zero exit code has 175 failures:

Test chip_sw_example_rom has 1 failures.

0.chip_sw_example_rom.1
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_example_rom/latest/run.log

  Analyzing: target //sw/device/tests:example_test_from_rom_sim_dv (12 packages loaded, 13 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests:example_test_from_rom_sim_dv' failed; build aborted: Target //sw/device/tests:example_test_from_rom_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests:example_test_from_rom_sim_dv (7e736f)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 14.274s, Critical Path: 0.07s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_example_manufacturer has 1 failures.

0.chip_sw_example_manufacturer.1
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_example_manufacturer/latest/run.log

  Analyzing: target @@+hooks+manufacturer_test_hooks//:example_test_sim_dv (1 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '@@+hooks+manufacturer_test_hooks//:example_test_sim_dv' failed; build aborted: Target @@+hooks+manufacturer_test_hooks//:example_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      @@+hooks+manufacturer_test_hooks//:example_test_sim_dv (7e736f)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 14.450s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_example_concurrency has 1 failures.

0.chip_sw_example_concurrency.1
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_example_concurrency/latest/run.log

  Analyzing: target //sw/device/tests:example_concurrency_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests:example_concurrency_test_sim_dv' failed; build aborted: Target //sw/device/tests:example_concurrency_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests:example_concurrency_test_sim_dv (7e736f)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 0.099s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_data_integrity_escalation has 1 failures.

0.chip_sw_data_integrity_escalation.1
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_data_integrity_escalation/latest/run.log

  Analyzing: target //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv (7e736f)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 103.747s, Critical Path: 0.02s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_sleep_pin_wake has 1 failures.

0.chip_sw_sleep_pin_wake.1
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_sleep_pin_wake/latest/run.log

  Computing main repo mapping:
  Loading:
  Loading: 0 packages loaded
  WARNING: Target pattern parsing failed.
  ERROR: Skipping '//sw/device/tests/sim_dv:sleep_pin_wake_test_sim_dv': no such target '//sw/device/tests/sim_dv:sleep_pin_wake_test_sim_dv': target 'sleep_pin_wake_test_sim_dv' not declared in package 'sw/device/tests/sim_dv' defined by /nightly/runs/opentitan/sw/device/tests/sim_dv/BUILD
  ERROR: no such target '//sw/device/tests/sim_dv:sleep_pin_wake_test_sim_dv': target 'sleep_pin_wake_test_sim_dv' not declared in package 'sw/device/tests/sim_dv' defined by /nightly/runs/opentitan/sw/device/tests/sim_dv/BUILD
  INFO: Elapsed time: 98.140s
  INFO: 0 processes.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

... and 170 more tests.

UVM_FATAL @ * us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat" has 8 failures:

Test chip_sw_aes_enc_jitter_en has 1 failures.

0.chip_sw_aes_enc_jitter_en.1
Line 431, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aes_enc_jitter_en/latest/run.log

  UVM_FATAL @  10.200001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_hmac_enc_jitter_en has 1 failures.

0.chip_sw_hmac_enc_jitter_en.1
Line 421, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_hmac_enc_jitter_en/latest/run.log

  UVM_FATAL @  10.200001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_keymgr_dpe_key_derivation_jitter_en has 1 failures.

0.chip_sw_keymgr_dpe_key_derivation_jitter_en.1
Line 418, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation_jitter_en/latest/run.log

  UVM_FATAL @  10.200001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_kmac_mode_kmac_jitter_en has 1 failures.

0.chip_sw_kmac_mode_kmac_jitter_en.1
Line 415, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_kmac_mode_kmac_jitter_en/latest/run.log

  UVM_FATAL @  10.200001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_aes_enc_jitter_en_reduced_freq has 1 failures.

0.chip_sw_aes_enc_jitter_en_reduced_freq.1
Line 416, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aes_enc_jitter_en_reduced_freq/latest/run.log

  UVM_FATAL @  10.200001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more tests.

UVM_ERROR @ * us: (chip_sw_base_vseq.sv:374) virtual_sequencer [chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInBootRom, TIMEOUT = * ns has 5 failures:

Test chip_sw_rstmgr_sw_req has 1 failures.

0.chip_sw_rstmgr_sw_req.1
Line 423, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rstmgr_sw_req/latest/run.log

  UVM_ERROR @ 12026.586846 us: (chip_sw_base_vseq.sv:374) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInBootRom, TIMEOUT = 12000000 ns

  UVM_INFO @ 12026.586846 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_rstmgr_cpu_info has 1 failures.

0.chip_sw_rstmgr_cpu_info.1
Line 417, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rstmgr_cpu_info/latest/run.log

  UVM_ERROR @ 20026.586846 us: (chip_sw_base_vseq.sv:374) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInBootRom, TIMEOUT = 20000000 ns

  UVM_INFO @ 20026.586846 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_aes_entropy has 1 failures.

0.chip_sw_aes_entropy.1
Line 419, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aes_entropy/latest/run.log

  UVM_ERROR @ 15026.586846 us: (chip_sw_base_vseq.sv:374) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInBootRom, TIMEOUT = 15000000 ns

  UVM_INFO @ 15026.586846 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_kmac_mode_cshake has 1 failures.

0.chip_sw_kmac_mode_cshake.1
Line 417, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_kmac_mode_cshake/latest/run.log

  UVM_ERROR @ 12026.586846 us: (chip_sw_base_vseq.sv:374) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInBootRom, TIMEOUT = 12000000 ns

  UVM_INFO @ 12026.586846 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_kmac_mode_kmac has 1 failures.

0.chip_sw_kmac_mode_kmac.1
Line 417, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_kmac_mode_kmac/latest/run.log

  UVM_ERROR @ 12026.586846 us: (chip_sw_base_vseq.sv:374) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInBootRom, TIMEOUT = 12000000 ns

  UVM_INFO @ 12026.586846 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:489) [chip_sw_keymgr_dpe_key_derivation_vseq] Check failed keymgr_pkg::KeyWidth'(get_kmac_digest(kmac_key, data_arr)) == act_digest (* [*] vs * [*]) has 2 failures:

Test chip_sw_keymgr_dpe_key_derivation has 1 failures.

0.chip_sw_keymgr_dpe_key_derivation.1
Line 470, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation/latest/run.log

  UVM_ERROR @ 6999.344266 us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:489) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_dpe_key_derivation_vseq] Check failed keymgr_pkg::KeyWidth'(get_kmac_digest(kmac_key, data_arr)) == act_digest (20870546663505487993462425207876635025979720400420381864231422976139785287596 [0x2e244f90865b84d57dbb72cad6b7468f6c0dc4bfd92985b90fed02e3849a37ac] vs 2239713429223367701379108512752088194818008878579040911872115941158669310061 [0x4f3a20446474a9c157750a3f4181964a1ade6cf380bf0be795aadad6154d86d])
  UVM_INFO @ 6999.344266 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_keymgr_dpe_key_derivation_prod has 1 failures.

0.chip_sw_keymgr_dpe_key_derivation_prod.1
Line 466, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation_prod/latest/run.log

  UVM_ERROR @ 6999.344266 us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:489) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_dpe_key_derivation_vseq] Check failed keymgr_pkg::KeyWidth'(get_kmac_digest(kmac_key, data_arr)) == act_digest (12018845053894871086227066926217721068744092990583922708119958837933417125302 [0x1a926cdbfb0c7ffca6722c01964ee9137fdcb15cfdf36aa77c3ae549667b55b6] vs 49850771993318409980224837819013833643101862431824486601139925681054935403230 [0x6e36897cf0faee9ce76f4e42bb2715ff86a8daece0d15ef96591c81f85a7cade])
  UVM_INFO @ 6999.344266 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:521) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@44414) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 2 failures:

Test chip_jtag_csr_rw has 1 failures.

0.chip_jtag_csr_rw.1
Line 5670, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_jtag_csr_rw/latest/run.log

  UVM_ERROR @ 3683.408174 us: (cip_base_scoreboard.sv:521) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@44414) { a_addr: 'h30480000  a_data: 'h1f135537  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h36  a_opcode: 'h1  a_user: 'h248d9  d_param: 'h0  d_source: 'h36  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_source_is_overridden: 'h0  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 1, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 3683.408174 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_jtag_mem_access has 1 failures.

0.chip_jtag_mem_access.1
Line 5670, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_jtag_mem_access/latest/run.log

  UVM_ERROR @ 3683.408174 us: (cip_base_scoreboard.sv:521) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@44414) { a_addr: 'h30480000  a_data: 'h1f135537  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h36  a_opcode: 'h1  a_user: 'h248d9  d_param: 'h0  d_source: 'h36  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_source_is_overridden: 'h0  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 1, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 3683.408174 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:521) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_soc_mbx_reg_block, TL item: req: (cip_tl_seq_item@2485807) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_csr_aliasing has 1 failures.

0.chip_csr_aliasing.1
Line 265, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_csr_aliasing/latest/run.log

  UVM_ERROR @ 15714.694216 us: (cip_base_scoreboard.sv:521) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface chip_soc_mbx_reg_block, TL item: req: (cip_tl_seq_item@2485807) { a_addr: 'h146511a  a_data: 'hdf64788c  a_mask: 'h0  a_size: 'h1  a_param: 'h0  a_source: 'h84  a_opcode: 'h4  a_user: 'h26d1d  d_param: 'h0  d_source: 'h84  d_data: 'hffffffff  d_size: 'h1  d_opcode: 'h1  d_error: 'h1  d_sink: 'h0  d_user: 'h2aa  a_source_is_overridden: 'h0  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 15714.694216 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_vseq.sv:293) [chip_common_vseq] Check failed masked_data == exp_data (* [*] vs * [*]) addr * read out mismatch has 1 failures:
- Test chip_same_csr_outstanding has 1 failures.
  - 0.chip_same_csr_outstanding.1
    Line 265, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_same_csr_outstanding/latest/run.log
```
  UVM_ERROR @ 5130.274216 us: (cip_base_vseq.sv:293) [uvm_test_top.env.virtual_sequencer.chip_common_vseq] Check failed masked_data == exp_data (150 [0x96] vs 153 [0x99]) addr 0x30170014 read out mismatch
  UVM_INFO @ 5130.274216 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_base_vseq.sv:374) virtual_sequencer [chip_sw_all_escalation_resets_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns has 1 failures:
- Test chip_sw_all_escalation_resets has 1 failures.
  - 0.chip_sw_all_escalation_resets.1
    Line 441, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_all_escalation_resets/latest/run.log
```
  UVM_ERROR @ 16581.018304 us: (chip_sw_base_vseq.sv:374) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_all_escalation_resets_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 12000000 ns

  UVM_INFO @ 16581.018304 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_base_vseq.sv:374) virtual_sequencer [chip_sw_rstmgr_cnsty_fault_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns has 1 failures:
- Test chip_sw_rstmgr_rst_cnsty_escalation has 1 failures.
  - 0.chip_sw_rstmgr_rst_cnsty_escalation.1
    Line 642, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rstmgr_rst_cnsty_escalation/latest/run.log
```
  UVM_ERROR @ 16582.644066 us: (chip_sw_base_vseq.sv:374) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_rstmgr_cnsty_fault_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 12000000 ns

  UVM_INFO @ 16582.644066 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty has 1 failures:
- Test chip_sw_spi_device_pass_through_collision has 1 failures.
  - 0.chip_sw_spi_device_pass_through_collision.1
    Line 440, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_spi_device_pass_through_collision/latest/run.log
```
  UVM_ERROR @ 4571.533030 us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty
  UVM_INFO @ 4571.533030 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_base_vseq.sv:374) virtual_sequencer [chip_sw_otp_ctrl_escalation_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns has 1 failures:
- Test chip_sw_otp_ctrl_escalation has 1 failures.
  - 0.chip_sw_otp_ctrl_escalation.1
    Line 430, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_otp_ctrl_escalation/latest/run.log
```
  UVM_ERROR @ 16583.342246 us: (chip_sw_base_vseq.sv:374) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_otp_ctrl_escalation_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 12000000 ns

  UVM_INFO @ 16583.342246 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (sw_logger_if.sv:527) [rstmgr_alert_info_test_sim_dv(sw/device/tests/rstmgr_alert_info_test.c:859)] unexpected reset info * has 1 failures:
- Test chip_sw_rstmgr_alert_info has 1 failures.
  - 0.chip_sw_rstmgr_alert_info.1
    Line 432, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rstmgr_alert_info/latest/run.log
```
  UVM_FATAL @ 7085.280250 us: (sw_logger_if.sv:527) [rstmgr_alert_info_test_sim_dv(sw/device/tests/rstmgr_alert_info_test.c:859)] unexpected reset info 20
  UVM_INFO @ 7085.280250 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [rv_core_ibex_nmi_irq_test_sim_dv(sw/device/tests/rv_core_ibex_nmi_irq_test.c:172)] CHECK-fail: Timed out after * usec (* CPU cycles) waiting for nmi_fired has 1 failures:
- Test chip_sw_rv_core_ibex_nmi_irq has 1 failures.
  - 0.chip_sw_rv_core_ibex_nmi_irq.1
    Line 439, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rv_core_ibex_nmi_irq/latest/run.log
```
  UVM_ERROR @ 6407.746430 us: (sw_logger_if.sv:526) [rv_core_ibex_nmi_irq_test_sim_dv(sw/device/tests/rv_core_ibex_nmi_irq_test.c:172)] CHECK-fail: Timed out after 1000 usec (100000 CPU cycles) waiting for nmi_fired
  UVM_INFO @ 6407.746430 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[RamCtn0]] file kmac_app_rom_test_sim_dv.*.vmem could not be opened for r mode has 1 failures:
- Test chip_sw_kmac_app_rom has 1 failures.
  - 0.chip_sw_kmac_app_rom.1
    Line 431, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_kmac_app_rom/latest/run.log
```
  UVM_FATAL @  10.200001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[RamCtn0]] file kmac_app_rom_test_sim_dv.32.vmem could not be opened for r mode
  UVM_INFO @  10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:521) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@34941) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_tl_errors has 1 failures.

0.chip_tl_errors.1
Line 265, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_tl_errors/latest/run.log

  UVM_ERROR @ 3702.734216 us: (cip_base_scoreboard.sv:521) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@34941) { a_addr: 'h40784  a_data: 'h709dee66  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'ha  a_opcode: 'h4  a_user: 'h1829c  d_param: 'h0  d_source: 'ha  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_source_is_overridden: 'h0  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 3702.734216 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Error-[CNST-CIF] Constraints inconsistency failure has 1 failures:
- Test chip_padctrl_attributes has 1 failures.
  - 0.chip_padctrl_attributes.1
    Line 312, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_padctrl_attributes/latest/run.log
```
  Error-[CNST-CIF] Constraints inconsistency failure
  ../src/lowrisc_dv_dv_lib_0/dv_base_test.sv, 95
    Constraints are inconsistent and cannot be solved.
    Please check the inconsistent constraints being printed above and rewrite
    them.
```

UVM_FATAL @ * us: sequencer [sequencer] Item_done() called with no outstanding requests. Each call to item_done() must be paired with a previous call to get_next_item(). has 1 failures:

Test chip_sw_dma_abort has 1 failures.

0.chip_sw_dma_abort.1
Line 427, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_dma_abort/latest/run.log

  UVM_FATAL @ 4499.301322 us: uvm_test_top.env.m_spi_device_agents0.sequencer [uvm_test_top.env.m_spi_device_agents0.sequencer] Item_done() called with no outstanding requests. Each call to item_done() must be paired with a previous call to get_next_item().
  UVM_INFO @ 4499.301322 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: chip_soc_dbg_reg_block.soc_dbg_ctrl_jtag.jtag_trace_debug_policy_category reset value: * has 1 failures:
- Test chip_csr_hw_reset has 1 failures.
  - 0.chip_csr_hw_reset.1
    Line 285, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_csr_hw_reset/latest/run.log
```
  UVM_ERROR @ 6400.204334 us: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (99 [0x63] vs 0 [0x0]) Regname: chip_soc_dbg_reg_block.soc_dbg_ctrl_jtag.jtag_trace_debug_policy_category reset value: 0x0
  UVM_INFO @ 6400.204334 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: chip_reg_block.soc_dbg_ctrl_core.trace_debug_policy_category.category reset value: * has 1 failures:
- Test chip_csr_rw has 1 failures.
  - 0.chip_csr_rw.1
    Line 265, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_csr_rw/latest/run.log
```
  UVM_ERROR @ 3710.314216 us: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (99 [0x63] vs 0 [0x0]) Regname: chip_reg_block.soc_dbg_ctrl_core.trace_debug_policy_category.category reset value: 0x0
  UVM_INFO @ 3710.314216 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Offending '(tl_h_i[*].a_source[(IDW - *)-:STIDW] == '0)' has 1 failures:
- Test chip_csr_mem_rw_with_rand_reset has 1 failures.
  - 0.chip_csr_mem_rw_with_rand_reset.1
    Line 271, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_csr_mem_rw_with_rand_reset/latest/run.log
```
      Offending '(tl_h_i[0].a_source[(IDW - 1)-:STIDW] == '0)'
  UVM_ERROR @ 3702.454216 us: (tlul_socket_m1.sv:101) [ASSERT FAILED] idInRange
  UVM_INFO @ 3702.454216 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```