HMAC Simulation Results

Tuesday March 25 2025 17:10:18 UTC

GitHub Revision: 113d4d16b3

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke hmac_smoke 4.100s 1.189ms 1 1 100.00
V1 csr_hw_reset hmac_csr_hw_reset 1.550s 77.119us 1 1 100.00
V1 csr_rw hmac_csr_rw 1.490s 65.036us 1 1 100.00
V1 csr_bit_bash hmac_csr_bit_bash 4.700s 1.912ms 1 1 100.00
V1 csr_aliasing hmac_csr_aliasing 3.130s 728.374us 1 1 100.00
V1 csr_mem_rw_with_rand_reset hmac_csr_mem_rw_with_rand_reset 1.760s 57.619us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr hmac_csr_rw 1.490s 65.036us 1 1 100.00
hmac_csr_aliasing 3.130s 728.374us 1 1 100.00
V1 TOTAL 6 6 100.00
V2 long_msg hmac_long_msg 35.350s 14.003ms 1 1 100.00
V2 back_pressure hmac_back_pressure 9.840s 945.834us 1 1 100.00
V2 test_vectors hmac_test_sha256_vectors 6.710s 566.165us 1 1 100.00
hmac_test_sha384_vectors 14.240s 723.874us 1 1 100.00
hmac_test_sha512_vectors 14.450s 723.874us 1 1 100.00
hmac_test_hmac256_vectors 4.860s 546.414us 1 1 100.00
hmac_test_hmac384_vectors 6.570s 803.208us 1 1 100.00
hmac_test_hmac512_vectors 6.240s 676.790us 1 1 100.00
V2 burst_wr hmac_burst_wr 18.860s 7.354ms 1 1 100.00
V2 datapath_stress hmac_datapath_stress 2.794m 6.680ms 1 1 100.00
V2 error hmac_error 41.120s 17.177ms 1 1 100.00
V2 wipe_secret hmac_wipe_secret 19.450s 8.263ms 1 1 100.00
V2 save_and_restore hmac_smoke 4.100s 1.189ms 1 1 100.00
hmac_long_msg 35.350s 14.003ms 1 1 100.00
hmac_back_pressure 9.840s 945.834us 1 1 100.00
hmac_datapath_stress 2.794m 6.680ms 1 1 100.00
hmac_burst_wr 18.860s 7.354ms 1 1 100.00
hmac_stress_all 58.420s 22.796ms 1 1 100.00
V2 fifo_empty_status_interrupt hmac_smoke 4.100s 1.189ms 1 1 100.00
hmac_long_msg 35.350s 14.003ms 1 1 100.00
hmac_back_pressure 9.840s 945.834us 1 1 100.00
hmac_datapath_stress 2.794m 6.680ms 1 1 100.00
hmac_wipe_secret 19.450s 8.263ms 1 1 100.00
hmac_test_sha256_vectors 6.710s 566.165us 1 1 100.00
hmac_test_sha384_vectors 14.240s 723.874us 1 1 100.00
hmac_test_sha512_vectors 14.450s 723.874us 1 1 100.00
hmac_test_hmac256_vectors 4.860s 546.414us 1 1 100.00
hmac_test_hmac384_vectors 6.570s 803.208us 1 1 100.00
hmac_test_hmac512_vectors 6.240s 676.790us 1 1 100.00
V2 wide_digest_configurable_key_length hmac_smoke 4.100s 1.189ms 1 1 100.00
hmac_long_msg 35.350s 14.003ms 1 1 100.00
hmac_back_pressure 9.840s 945.834us 1 1 100.00
hmac_datapath_stress 2.794m 6.680ms 1 1 100.00
hmac_burst_wr 18.860s 7.354ms 1 1 100.00
hmac_error 41.120s 17.177ms 1 1 100.00
hmac_wipe_secret 19.450s 8.263ms 1 1 100.00
hmac_test_sha256_vectors 6.710s 566.165us 1 1 100.00
hmac_test_sha384_vectors 14.240s 723.874us 1 1 100.00
hmac_test_sha512_vectors 14.450s 723.874us 1 1 100.00
hmac_test_hmac256_vectors 4.860s 546.414us 1 1 100.00
hmac_test_hmac384_vectors 6.570s 803.208us 1 1 100.00
hmac_test_hmac512_vectors 6.240s 676.790us 1 1 100.00
hmac_stress_all 58.420s 22.796ms 1 1 100.00
V2 stress_all hmac_stress_all 58.420s 22.796ms 1 1 100.00
V2 alert_test hmac_alert_test 1.330s 39.869us 1 1 100.00
V2 intr_test hmac_intr_test 1.290s 38.994us 1 1 100.00
V2 tl_d_oob_addr_access hmac_tl_errors 2.340s 370.455us 1 1 100.00
V2 tl_d_illegal_access hmac_tl_errors 2.340s 370.455us 1 1 100.00
V2 tl_d_outstanding_access hmac_csr_hw_reset 1.550s 77.119us 1 1 100.00
hmac_csr_rw 1.490s 65.036us 1 1 100.00
hmac_csr_aliasing 3.130s 728.374us 1 1 100.00
hmac_same_csr_outstanding 1.910s 211.037us 1 1 100.00
V2 tl_d_partial_access hmac_csr_hw_reset 1.550s 77.119us 1 1 100.00
hmac_csr_rw 1.490s 65.036us 1 1 100.00
hmac_csr_aliasing 3.130s 728.374us 1 1 100.00
hmac_same_csr_outstanding 1.910s 211.037us 1 1 100.00
V2 TOTAL 17 17 100.00
V2S tl_intg_err hmac_sec_cm 1.630s 140.244us 1 1 100.00
hmac_tl_intg_err 2.340s 371.413us 1 1 100.00
V2S sec_cm_bus_integrity hmac_tl_intg_err 2.340s 371.413us 1 1 100.00
V2S TOTAL 2 2 100.00
V3 write_config_and_secret_key_during_msg_wr hmac_smoke 4.100s 1.189ms 1 1 100.00
V3 stress_reset hmac_stress_reset 3.690s 779.791us 1 1 100.00
V3 stress_all_with_rand_reset hmac_stress_all_with_rand_reset 21.730s 7.673ms 1 1 100.00
V3 TOTAL 2 2 100.00
Unmapped tests hmac_directed 1.470s 48.431us 1 1 100.00
TOTAL 28 28 100.00