DMA Simulation Results

Wednesday March 26 2025 17:03:12 UTC

GitHub Revision: 0fcb0d1431

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	dma_memory_smoke	dma_memory_smoke	6.000s	1.230ms	1	1	100.00
V1	dma_handshake_smoke	dma_handshake_smoke	6.000s	1.284ms	1	1	100.00
V1	dma_generic_smoke	dma_generic_smoke	6.000s	1.573ms	1	1	100.00
V1	csr_hw_reset	dma_csr_hw_reset	4.000s	84.741us	1	1	100.00
V1	csr_rw	dma_csr_rw	4.000s	91.341us	1	1	100.00
V1	csr_bit_bash	dma_csr_bit_bash	9.000s	3.735ms	1	1	100.00
V1	csr_aliasing	dma_csr_aliasing	6.000s	1.373ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	dma_csr_mem_rw_with_rand_reset	4.000s	136.241us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	dma_csr_rw	4.000s	91.341us	1	1	100.00
		dma_csr_aliasing	6.000s	1.373ms	1	1	100.00
V1		TOTAL			8	8	100.00
V2	dma_memory_region_lock	dma_memory_region_lock	37.000s	15.846ms	1	1	100.00
V2	dma_handshake_stress	dma_handshake_stress	6.117m	207.697ms	1	1	100.00
V2	dma_memory_stress	dma_memory_stress	25.983m	902.889ms	1	1	100.00
V2	dma_generic_stress	dma_generic_stress	4.517m	150.731ms	1	1	100.00
V2	dma_handshake_mem_buffer_overflow	dma_handshake_stress	6.117m	207.697ms	1	1	100.00
V2	dma_abort	dma_abort	12.000s	4.510ms	1	1	100.00
V2	dma_stress_all	dma_stress_all	2.467m	67.501ms	1	1	100.00
V2	intr_test	dma_intr_test	3.000s	50.791us	1	1	100.00
V2	tl_d_oob_addr_access	dma_tl_errors	4.000s	315.941us	1	1	100.00
V2	tl_d_illegal_access	dma_tl_errors	4.000s	315.941us	1	1	100.00
V2	tl_d_outstanding_access	dma_csr_hw_reset	4.000s	84.741us	1	1	100.00
		dma_csr_rw	4.000s	91.341us	1	1	100.00
		dma_csr_aliasing	6.000s	1.373ms	1	1	100.00
		dma_same_csr_outstanding	4.000s	306.741us	1	1	100.00
V2	tl_d_partial_access	dma_csr_hw_reset	4.000s	84.741us	1	1	100.00
		dma_csr_rw	4.000s	91.341us	1	1	100.00
		dma_csr_aliasing	6.000s	1.373ms	1	1	100.00
		dma_same_csr_outstanding	4.000s	306.741us	1	1	100.00
V2		TOTAL			9	9	100.00
V2S	dma_illegal_addr_range	dma_mem_enabled	29.000s	1.776ms	1	1	100.00
		dma_generic_stress	4.517m	150.731ms	1	1	100.00
		dma_handshake_stress	6.117m	207.697ms	1	1	100.00
V2S	tl_intg_err	dma_tl_intg_err	4.000s	547.241us	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	dma_short_transfer	2.050m	76.319ms	1	1	100.00
		dma_longer_transfer	10.000s	2.654ms	1	1	100.00
		TOTAL			21	21	100.00