CHIP Simulation Results

Thursday March 27 2025 17:08:29 UTC

GitHub Revision: `b5827114c9`

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	chip_sw_uart_tx_rx	chip_sw_uart_tx_rx	1.201m		0	1	0.00
V1	chip_sw_uart_rx_overflow	chip_sw_uart_tx_rx	1.201m		0	1	0.00
V1	chip_sw_uart_rand_baudrate	chip_sw_uart_rand_baudrate	11.033s		0	1	0.00
V1	chip_sw_uart_tx_rx_alt_clk_freq	chip_sw_uart_tx_rx_alt_clk_freq	11.043s		0	1	0.00
		chip_sw_uart_tx_rx_alt_clk_freq_low_speed	10.042s		0	1	0.00
V1	chip_sw_gpio_out	chip_sw_gpio	5.362m	5.110ms	1	1	100.00
V1	chip_sw_gpio_in	chip_sw_gpio	5.362m	5.110ms	1	1	100.00
V1	chip_sw_gpio_irq	chip_sw_gpio	5.362m	5.110ms	1	1	100.00
V1	chip_sw_example_tests	chip_sw_example_rom	1.469m		0	1	0.00
		chip_sw_example_manufacturer	1.352m		0	1	0.00
		chip_sw_example_concurrency	3.291m	4.019ms	1	1	100.00
		chip_sw_uart_smoketest_signed	13.094s		0	1	0.00
V1	csr_hw_reset	chip_csr_hw_reset	3.990m	6.409ms	0	1	0.00
V1	csr_rw	chip_csr_rw	2.620m	3.806ms	0	1	0.00
V1	csr_bit_bash	chip_csr_bit_bash	5.005m	5.300ms	1	1	100.00
V1	csr_aliasing	chip_csr_aliasing	19.563m	11.903ms	0	1	0.00
V1	csr_mem_rw_with_rand_reset	chip_csr_mem_rw_with_rand_reset	2.545m	3.702ms	0	1	0.00
V1	regwen_csr_and_corresponding_lockable_csr	chip_csr_aliasing	19.563m	11.903ms	0	1	0.00
		chip_csr_rw	2.620m	3.806ms	0	1	0.00
V1	xbar_smoke	xbar_smoke	16.850s	49.909us	1	1	100.00
V1		TOTAL			4	15	26.67
V2	chip_sw_spi_device_flash_mode	chip_sw_uart_tx_rx_bootstrap	14.020s		0	1	0.00
V2	chip_sw_spi_device_pass_through	chip_sw_spi_device_pass_through	8.036m	7.609ms	1	1	100.00
V2	chip_sw_spi_device_pass_through_collision	chip_sw_spi_device_pass_through_collision	3.715m	4.184ms	0	1	0.00
V2	chip_sw_spi_device_tpm	chip_sw_spi_device_tpm	10.039s		0	1	0.00
V2	chip_sw_spi_host_tx_rx	chip_sw_spi_host_tx_rx	10.043s		0	1	0.00
V2	chip_sw_i2c_host_tx_rx	chip_sw_i2c_host_tx_rx	10.042s		0	1	0.00
V2	chip_sw_i2c_device_tx_rx	chip_sw_i2c_device_tx_rx	10.041s		0	1	0.00
V2	chip_pin_mux	chip_padctrl_attributes	3.420s		0	1	0.00
V2	chip_padctrl_attributes	chip_padctrl_attributes	3.420s		0	1	0.00
V2	chip_sw_sleep_pin_wake	chip_sw_sleep_pin_wake	1.285m		0	1	0.00
V2	chip_sw_sleep_pin_retention	chip_sw_sleep_pin_retention	1.101m		0	1	0.00
V2	chip_sw_data_integrity	chip_sw_data_integrity_escalation	1.201m		0	1	0.00
V2	chip_sw_instruction_integrity	chip_sw_data_integrity_escalation	1.201m		0	1	0.00
V2	chip_jtag_csr_rw	chip_jtag_csr_rw	2.541m	3.683ms	0	1	0.00
V2	chip_jtag_mem_access	chip_jtag_mem_access	2.369m	3.683ms	0	1	0.00
V2	chip_rv_dm_ndm_reset_req	chip_rv_dm_ndm_reset_req	11.031s		0	1	0.00
V2	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	11.031s		0	1	0.00
V2	chip_rv_dm_access_after_wakeup	chip_sw_rv_dm_access_after_wakeup	10.031s		0	1	0.00
V2	chip_rv_dm_lc_disabled	chip_rv_dm_lc_disabled	11.006m	17.314ms	1	1	100.00
V2	chip_sw_timer	chip_sw_rv_timer_irq	4.468m	5.042ms	1	1	100.00
V2	chip_sw_aon_timer_wakeup_irq	chip_sw_aon_timer_irq	11.029s		0	1	0.00
V2	chip_sw_aon_timer_wdog_bark_irq	chip_sw_aon_timer_irq	11.029s		0	1	0.00
V2	chip_sw_aon_timer_wdog_lc_escalate	chip_sw_aon_timer_wdog_lc_escalate	11.055s		0	1	0.00
V2	chip_sw_aon_timer_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	11.038s		0	1	0.00
V2	chip_sw_aon_timer_sleep_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	11.038s		0	1	0.00
V2	chip_sw_aon_timer_sleep_wdog_sleep_pause	chip_sw_aon_timer_sleep_wdog_sleep_pause	11.025s		0	1	0.00
V2	chip_sw_plic_all_irqs	chip_plic_all_irqs	10.046s		0	1	0.00
V2	chip_sw_plic_sw_irq	chip_sw_plic_sw_irq	3.287m	3.980ms	1	1	100.00
V2	chip_sw_clkmgr_idle_trans	chip_sw_otbn_randomness	4.006m	4.343ms	1	1	100.00
		chip_sw_aes_idle	3.369m	3.990ms	1	1	100.00
		chip_sw_hmac_enc_idle	11.018s		0	1	0.00
		chip_sw_kmac_idle	3.219m	3.966ms	1	1	100.00
V2	chip_sw_clkmgr_off_trans	chip_sw_clkmgr_off_aes_trans	11.055s		0	1	0.00
		chip_sw_clkmgr_off_hmac_trans	11.053s		0	1	0.00
		chip_sw_clkmgr_off_kmac_trans	11.053s		0	1	0.00
		chip_sw_clkmgr_off_otbn_trans	11.052s		0	1	0.00
V2	chip_sw_clkmgr_div	chip_sw_clkmgr_external_clk_src_for_lc	11.052s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	11.047s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	11.046s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	10.046s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	11.055s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	11.055s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	11.054s		0	1	0.00
V2	chip_sw_clkmgr_external_clk_src_for_lc	chip_sw_clkmgr_external_clk_src_for_lc	11.052s		0	1	0.00
V2	chip_sw_clkmgr_external_clk_src_for_sw	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	11.047s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	11.046s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	10.046s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	11.055s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	11.055s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	11.054s		0	1	0.00
V2	chip_sw_clkmgr_jitter	chip_sw_otbn_ecdsa_op_irq_jitter_en	12.042s		0	1	0.00
		chip_sw_aes_enc_jitter_en	42.050s	10.200us	0	1	0.00
		chip_sw_edn_entropy_reqs_jitter	11.023s		0	1	0.00
		chip_sw_hmac_enc_jitter_en	43.370s	10.200us	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	42.660s	10.200us	0	1	0.00
		chip_sw_kmac_mode_kmac_jitter_en	43.830s	10.200us	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	11.042s		0	1	0.00
		chip_sw_clkmgr_jitter	2.901m	3.936ms	1	1	100.00
V2	chip_sw_clkmgr_extended_range	chip_sw_clkmgr_jitter_reduced_freq	3.064m	4.016ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq	11.037s		0	1	0.00
		chip_sw_aes_enc_jitter_en_reduced_freq	43.780s	10.200us	0	1	0.00
		chip_sw_hmac_enc_jitter_en_reduced_freq	42.690s	10.200us	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en_reduced_freq	43.170s	10.200us	0	1	0.00
		chip_sw_kmac_mode_kmac_jitter_en_reduced_freq	44.620s	10.200us	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq	11.019s		0	1	0.00
		chip_sw_csrng_edn_concurrency_reduced_freq	11.016s		0	1	0.00
V2	chip_sw_clkmgr_deep_sleep_frequency	chip_sw_ast_clk_outputs	11.031s		0	1	0.00
V2	chip_sw_clkmgr_sleep_frequency	chip_sw_clkmgr_sleep_frequency	11.047s		0	1	0.00
V2	chip_sw_clkmgr_reset_frequency	chip_sw_clkmgr_reset_frequency	11.055s		0	1	0.00
V2	chip_sw_clkmgr_escalation_reset	chip_sw_all_escalation_resets	17.488m	13.181ms	1	1	100.00
V2	chip_sw_pwrmgr_external_full_reset	chip_sw_pwrmgr_full_aon_reset	10.012s		0	1	0.00
V2	chip_sw_pwrmgr_sleep_all_reset_reqs	chip_sw_aon_timer_wdog_bite_reset	11.038s		0	1	0.00
V2	chip_sw_pwrmgr_wdog_reset	chip_sw_pwrmgr_wdog_reset	11.060s		0	1	0.00
V2	chip_sw_pwrmgr_aon_power_glitch_reset	chip_sw_pwrmgr_full_aon_reset	10.012s		0	1	0.00
V2	chip_sw_pwrmgr_main_power_glitch_reset	chip_sw_pwrmgr_main_power_glitch_reset	11.013s		0	1	0.00
V2	chip_sw_pwrmgr_random_sleep_power_glitch_reset	chip_sw_pwrmgr_random_sleep_power_glitch_reset	11.009s		0	1	0.00
V2	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	11.010s		0	1	0.00
V2	chip_sw_pwrmgr_sleep_power_glitch_reset	chip_sw_pwrmgr_sleep_power_glitch_reset	10.012s		0	1	0.00
V2	chip_sw_pwrmgr_sleep_disabled	chip_sw_pwrmgr_sleep_disabled	10.021s		0	1	0.00
V2	chip_sw_pwrmgr_escalation_reset	chip_sw_all_escalation_resets	17.488m	13.181ms	1	1	100.00
V2	chip_sw_rstmgr_sys_reset_info	chip_rv_dm_ndm_reset_req	11.031s		0	1	0.00
V2	chip_sw_rstmgr_cpu_info	chip_sw_rstmgr_cpu_info	21.592m	20.027ms	0	1	0.00
V2	chip_sw_rstmgr_sw_req_reset	chip_sw_rstmgr_sw_req	13.919m	12.027ms	0	1	0.00
V2	chip_sw_rstmgr_alert_info	chip_sw_rstmgr_alert_info	6.132m	6.531ms	0	1	0.00
V2	chip_sw_rstmgr_sw_rst	chip_sw_rstmgr_sw_rst	3.032m	3.958ms	1	1	100.00
V2	chip_sw_rstmgr_escalation_reset	chip_sw_all_escalation_resets	17.488m	13.181ms	1	1	100.00
V2	chip_sw_alert_handler_alerts	chip_sw_alert_test	11.016s		0	1	0.00
V2	chip_sw_alert_handler_escalations	chip_sw_alert_handler_escalation	11.017s		0	1	0.00
V2	chip_sw_all_escalation_resets	chip_sw_all_escalation_resets	17.488m	13.181ms	1	1	100.00
V2	chip_sw_alert_handler_irqs	chip_plic_all_irqs	10.046s		0	1	0.00
V2	chip_sw_alert_handler_entropy	chip_sw_alert_handler_entropy	10.022s		0	1	0.00
V2	chip_sw_alert_handler_crashdump	chip_sw_rstmgr_alert_info	6.132m	6.531ms	0	1	0.00
V2	chip_sw_alert_handler_ping_timeout	chip_sw_alert_handler_ping_timeout	11.017s		0	1	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_alerts	chip_sw_alert_handler_lpg_sleep_mode_alerts	10.015s		0	1	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_pings	chip_sw_alert_handler_lpg_sleep_mode_pings	10.023s		0	1	0.00
V2	chip_sw_alert_handler_lpg_clock_off	chip_sw_alert_handler_lpg_clkoff	10.023s		0	1	0.00
V2	chip_sw_alert_handler_lpg_reset_toggle	chip_sw_alert_handler_lpg_reset_toggle	10.023s		0	1	0.00
V2	chip_sw_alert_handler_reverse_ping_in_deep_sleep	chip_sw_alert_handler_reverse_ping_in_deep_sleep	10.016s		0	1	0.00
V2	chip_sw_lc_ctrl_alert_handler_escalation	chip_sw_alert_handler_escalation	11.017s		0	1	0.00
V2	chip_sw_lc_ctrl_jtag_access	chip_sw_lc_ctrl_transition	11.033s		0	1	0.00
V2	chip_sw_lc_ctrl_otp_hw_cfg	chip_sw_lc_ctrl_otp_hw_cfg	13.029s		0	1	0.00
V2	chip_sw_lc_ctrl_init	chip_sw_lc_ctrl_transition	11.033s		0	1	0.00
V2	chip_sw_lc_ctrl_transitions	chip_sw_lc_ctrl_transition	11.033s		0	1	0.00
V2	chip_sw_lc_ctrl_kmac_req	chip_sw_lc_ctrl_transition	11.033s		0	1	0.00
V2	chip_sw_lc_ctrl_key_div	chip_sw_keymgr_dpe_key_derivation_prod	5.587m	6.501ms	0	1	0.00
V2	chip_sw_lc_ctrl_broadcast	chip_sw_otp_ctrl_lc_signals_test_unlocked0	12.038s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_dev	11.034s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_prod	10.032s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_rma	11.037s		0	1	0.00
		chip_sw_lc_ctrl_transition	11.033s		0	1	0.00
		chip_sw_keymgr_dpe_key_derivation	5.924m	6.501ms	0	1	0.00
		chip_sw_rom_ctrl_integrity_check	8.098m	11.340ms	1	1	100.00
		chip_sw_sram_ctrl_execution_main	11.041s		0	1	0.00
		chip_prim_tl_access	8.392m	13.660ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_lc	11.052s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	11.047s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	11.046s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	10.046s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	11.055s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	11.055s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	11.054s		0	1	0.00
		chip_rv_dm_lc_disabled	11.006m	17.314ms	1	1	100.00
V2	chip_sw_aes_enc	chip_sw_aes_enc	3.557m	4.080ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	42.050s	10.200us	0	1	0.00
V2	chip_sw_aes_entropy	chip_sw_aes_entropy	15.651m	15.027ms	0	1	0.00
V2	chip_sw_aes_idle	chip_sw_aes_idle	3.369m	3.990ms	1	1	100.00
V2	chip_sw_hmac_enc	chip_sw_hmac_enc	3.564m	4.081ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	43.370s	10.200us	0	1	0.00
V2	chip_sw_hmac_idle	chip_sw_hmac_enc_idle	11.018s		0	1	0.00
V2	chip_sw_kmac_enc	chip_sw_kmac_mode_cshake	12.022m	12.027ms	0	1	0.00
		chip_sw_kmac_mode_kmac	12.178m	12.027ms	0	1	0.00
		chip_sw_kmac_mode_kmac_jitter_en	43.830s	10.200us	0	1	0.00
V2	chip_sw_kmac_app_keymgr	chip_sw_keymgr_dpe_key_derivation	5.924m	6.501ms	0	1	0.00
V2	chip_sw_kmac_app_lc	chip_sw_lc_ctrl_transition	11.033s		0	1	0.00
V2	chip_sw_kmac_app_rom	chip_sw_kmac_app_rom	36.430s	10.200us	0	1	0.00
V2	chip_sw_kmac_entropy	chip_sw_kmac_entropy	14.042s		0	1	0.00
V2	chip_sw_kmac_idle	chip_sw_kmac_idle	3.219m	3.966ms	1	1	100.00
V2	chip_sw_entropy_src_csrng	chip_sw_entropy_src_csrng	11.020s		0	1	0.00
V2	chip_sw_csrng_edn_cmd	chip_sw_entropy_src_csrng	11.020s		0	1	0.00
V2	chip_sw_csrng_fuse_en_sw_app_read	chip_sw_csrng_fuse_en_sw_app_read_test	11.022s		0	1	0.00
V2	chip_sw_csrng_known_answer_tests	chip_sw_csrng_kat_test	3.407m	3.999ms	1	1	100.00
V2	chip_sw_edn_entropy_reqs	chip_sw_csrng_edn_concurrency	11.027s		0	1	0.00
		chip_sw_edn_entropy_reqs	11.019s		0	1	0.00
V2	chip_sw_keymgr_dpe_key_derivation	chip_sw_keymgr_dpe_key_derivation	5.924m	6.501ms	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	42.660s	10.200us	0	1	0.00
V2	chip_sw_otbn_op	chip_sw_otbn_ecdsa_op_irq	13.051s		0	1	0.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	12.042s		0	1	0.00
V2	chip_sw_otbn_rnd_entropy	chip_sw_otbn_randomness	4.006m	4.343ms	1	1	100.00
V2	chip_sw_otbn_urnd_entropy	chip_sw_otbn_randomness	4.006m	4.343ms	1	1	100.00
V2	chip_sw_otbn_idle	chip_sw_otbn_randomness	4.006m	4.343ms	1	1	100.00
V2	chip_sw_otbn_mem_scramble	chip_sw_otbn_mem_scramble	11.039s		0	1	0.00
V2	chip_sw_rom_access	chip_sw_rom_ctrl_integrity_check	8.098m	11.340ms	1	1	100.00
V2	chip_sw_rom_ctrl_integrity_check	chip_sw_rom_ctrl_integrity_check	8.098m	11.340ms	1	1	100.00
V2	chip_sw_sram_scrambled_access	chip_sw_sram_ctrl_scrambled_access	11.028s		0	1	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	11.042s		0	1	0.00
V2	chip_sw_sram_execution	chip_sw_sram_ctrl_execution_main	11.041s		0	1	0.00
V2	chip_sw_sram_lc_escalation	chip_sw_all_escalation_resets	17.488m	13.181ms	1	1	100.00
		chip_sw_data_integrity_escalation	1.201m		0	1	0.00
V2	chip_otp_ctrl_init	chip_sw_lc_ctrl_transition	11.033s		0	1	0.00
V2	chip_sw_otp_ctrl_keys	chip_sw_otbn_mem_scramble	11.039s		0	1	0.00
		chip_sw_keymgr_dpe_key_derivation	5.924m	6.501ms	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access	11.028s		0	1	0.00
		chip_sw_rv_core_ibex_icache_invalidate	12.039s		0	1	0.00
V2	chip_sw_otp_ctrl_entropy	chip_sw_otbn_mem_scramble	11.039s		0	1	0.00
		chip_sw_keymgr_dpe_key_derivation	5.924m	6.501ms	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access	11.028s		0	1	0.00
		chip_sw_rv_core_ibex_icache_invalidate	12.039s		0	1	0.00
V2	chip_sw_otp_ctrl_program	chip_sw_lc_ctrl_transition	11.033s		0	1	0.00
V2	chip_sw_otp_ctrl_program_error	chip_sw_lc_ctrl_program_error	11.031s		0	1	0.00
V2	chip_sw_otp_ctrl_hw_cfg	chip_sw_lc_ctrl_otp_hw_cfg	13.029s		0	1	0.00
V2	chip_sw_otp_ctrl_lc_signals	chip_sw_otp_ctrl_lc_signals_test_unlocked0	12.038s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_dev	11.034s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_prod	10.032s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_rma	11.037s		0	1	0.00
		chip_sw_lc_ctrl_transition	11.033s		0	1	0.00
		chip_prim_tl_access	8.392m	13.660ms	1	1	100.00
V2	chip_sw_otp_prim_tl_access	chip_prim_tl_access	8.392m	13.660ms	1	1	100.00
V2	chip_sw_otp_ctrl_nvm_cnt	chip_sw_otp_ctrl_nvm_cnt	11.030s		0	1	0.00
V2	chip_sw_otp_ctrl_sw_parts	chip_sw_otp_ctrl_sw_parts	11.032s		0	1	0.00
V2	chip_sw_ast_clk_outputs	chip_sw_ast_clk_outputs	11.031s		0	1	0.00
V2	chip_sw_ast_sys_clk_jitter	chip_sw_otbn_ecdsa_op_irq_jitter_en	12.042s		0	1	0.00
		chip_sw_aes_enc_jitter_en	42.050s	10.200us	0	1	0.00
		chip_sw_edn_entropy_reqs_jitter	11.023s		0	1	0.00
		chip_sw_hmac_enc_jitter_en	43.370s	10.200us	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	42.660s	10.200us	0	1	0.00
		chip_sw_kmac_mode_kmac_jitter_en	43.830s	10.200us	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	11.042s		0	1	0.00
		chip_sw_clkmgr_jitter	2.901m	3.936ms	1	1	100.00
V2	chip_sw_ast_alerts	chip_sw_sensor_ctrl_alert	10.043s		0	1	0.00
V2	chip_sw_sensor_ctrl_ast_alerts	chip_sw_sensor_ctrl_alert	10.043s		0	1	0.00
		chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	10.038s		0	1	0.00
V2	chip_sw_sensor_ctrl_ast_status	chip_sw_sensor_ctrl_status	10.039s		0	1	0.00
V2	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	10.038s		0	1	0.00
V2	chip_sw_soc_proxy_external_reset_requests	chip_sw_soc_proxy_smoketest	11.010s		0	1	0.00
V2	chip_sw_soc_proxy_external_irqs	chip_sw_soc_proxy_smoketest	11.010s		0	1	0.00
V2	chip_sw_soc_proxy_external_alerts	chip_sw_soc_proxy_external_alerts	11.013s		0	1	0.00
V2	chip_sw_soc_proxy_external_wakeup_requests	chip_sw_soc_proxy_external_wakeup	11.028s		0	1	0.00
V2	chip_sw_soc_proxy_gpios	chip_sw_soc_proxy_gpios	11.033s		0	1	0.00
V2	chip_sw_nmi_irq	chip_sw_rv_core_ibex_nmi_irq	6.663m	5.103ms	0	1	0.00
V2	chip_sw_rv_core_ibex_rnd	chip_sw_rv_core_ibex_rnd	3.690m	4.140ms	1	1	100.00
V2	chip_sw_rv_core_ibex_address_translation	chip_sw_rv_core_ibex_address_translation	3.681m	4.160ms	1	1	100.00
V2	chip_sw_rv_core_ibex_icache_scrambled_access	chip_sw_rv_core_ibex_icache_invalidate	12.039s		0	1	0.00
V2	chip_sw_rv_core_ibex_fault_dump	chip_sw_rstmgr_cpu_info	21.592m	20.027ms	0	1	0.00
V2	chip_sw_rv_core_ibex_double_fault	chip_sw_rstmgr_cpu_info	21.592m	20.027ms	0	1	0.00
V2	chip_sw_smoketest	chip_sw_aes_smoketest	3.098m	4.080ms	1	1	100.00
		chip_sw_aon_timer_smoketest	19.122s		0	1	0.00
		chip_sw_clkmgr_smoketest	11.081s		0	1	0.00
		chip_sw_csrng_smoketest	17.103s		0	1	0.00
		chip_sw_gpio_smoketest	3.098m	4.094ms	1	1	100.00
		chip_sw_hmac_smoketest	14.066s		0	1	0.00
		chip_sw_kmac_smoketest	12.055s		0	1	0.00
		chip_sw_otbn_smoketest	13.055s		0	1	0.00
		chip_sw_otp_ctrl_smoketest	12.050s		0	1	0.00
		chip_sw_rv_plic_smoketest	17.081s		0	1	0.00
		chip_sw_rv_timer_smoketest	4.261m	5.042ms	1	1	100.00
		chip_sw_rstmgr_smoketest	13.053s		0	1	0.00
		chip_sw_sram_ctrl_smoketest	12.041s		0	1	0.00
		chip_sw_uart_smoketest	3.135m	4.080ms	1	1	100.00
V2	chip_sw_rom_functests	rom_keymgr_functest	11.087s		0	1	0.00
V2	chip_sw_signed	chip_sw_uart_smoketest_signed	13.094s		0	1	0.00
V2	chip_sw_boot	chip_sw_uart_tx_rx_bootstrap	14.020s		0	1	0.00
V2	chip_sw_secure_boot	base_rom_e2e_smoke	11.018s		0	1	0.00
V2	chip_lc_scrap	chip_sw_lc_ctrl_rma_to_scrap	2.951m	4.375ms	1	1	100.00
		chip_sw_lc_ctrl_raw_to_scrap	3.077m	4.656ms	1	1	100.00
		chip_sw_lc_ctrl_test_locked0_to_scrap	3.416m	4.656ms	1	1	100.00
		chip_sw_lc_ctrl_rand_to_scrap	2.999m	4.656ms	1	1	100.00
V2	chip_lc_test_locked	chip_sw_lc_walkthrough_testunlocks	10.034s		0	1	0.00
		chip_rv_dm_lc_disabled	11.006m	17.314ms	1	1	100.00
V2	chip_sw_lc_walkthrough	chip_sw_lc_walkthrough_dev	13.020s		0	1	0.00
		chip_sw_lc_walkthrough_prod	11.018s		0	1	0.00
		chip_sw_lc_walkthrough_prodend	10.038s		0	1	0.00
		chip_sw_lc_walkthrough_rma	10.038s		0	1	0.00
		chip_sw_lc_walkthrough_testunlocks	10.034s		0	1	0.00
V2	chip_sw_lc_ctrl_volatile_raw_unlock	chip_sw_lc_ctrl_volatile_raw_unlock	11.046s		0	1	0.00
		chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	10.030s		0	1	0.00
		rom_volatile_raw_unlock	10.089s		0	1	0.00
V2	chip_sw_rom_raw_unlock	rom_raw_unlock	10.088s		0	1	0.00
V2	chip_sw_exit_test_unlocked_bootstrap	chip_sw_exit_test_unlocked_bootstrap	11.036s		0	1	0.00
V2	chip_sw_inject_scramble_seed	chip_sw_inject_scramble_seed	12.038s		0	1	0.00
V2	tl_d_oob_addr_access	chip_tl_errors	2.367m	3.703ms	0	1	0.00
V2	tl_d_illegal_access	chip_tl_errors	2.367m	3.703ms	0	1	0.00
V2	tl_d_outstanding_access	chip_csr_aliasing	19.563m	11.903ms	0	1	0.00
		chip_same_csr_outstanding	4.209m	4.883ms	0	1	0.00
		chip_csr_hw_reset	3.990m	6.409ms	0	1	0.00
		chip_csr_rw	2.620m	3.806ms	0	1	0.00
V2	tl_d_partial_access	chip_csr_aliasing	19.563m	11.903ms	0	1	0.00
		chip_same_csr_outstanding	4.209m	4.883ms	0	1	0.00
		chip_csr_hw_reset	3.990m	6.409ms	0	1	0.00
		chip_csr_rw	2.620m	3.806ms	0	1	0.00
V2	xbar_base_random_sequence	xbar_random	3.150m	510.675us	1	1	100.00
V2	xbar_random_delay	xbar_smoke_zero_delays	7.610s	10.734us	1	1	100.00
		xbar_smoke_large_delays	3.638m	2.073ms	1	1	100.00
		xbar_smoke_slow_rsp	4.477m	1.822ms	1	1	100.00
		xbar_random_zero_delays	1.349m	74.809us	1	1	100.00
		xbar_random_large_delays	22.655m	12.543ms	1	1	100.00
		xbar_random_slow_rsp	36.312m	14.519ms	1	1	100.00
V2	xbar_unmapped_address	xbar_unmapped_addr	1.764m	221.078us	1	1	100.00
		xbar_error_and_unmapped_addr	1.597m	221.797us	1	1	100.00
V2	xbar_error_cases	xbar_error_random	3.001m	510.675us	1	1	100.00
		xbar_error_and_unmapped_addr	1.597m	221.797us	1	1	100.00
V2	xbar_all_access_same_device	xbar_access_same_device	5.046m	835.777us	1	1	100.00
		xbar_access_same_device_slow_rsp	59.008m	24.061ms	1	1	100.00
V2	xbar_all_hosts_use_same_source_id	xbar_same_source	1.050m	199.661us	1	1	100.00
V2	xbar_stress_all	xbar_stress_all	10.748m	1.684ms	1	1	100.00
		xbar_stress_all_with_error	9.837m	1.684ms	1	1	100.00
V2	xbar_stress_with_reset	xbar_stress_all_with_rand_reset	28.371m	2.777ms	1	1	100.00
		xbar_stress_all_with_reset_error	23.582m	2.777ms	1	1	100.00
V2	rom_e2e_smoke	rom_e2e_smoke	10.016s		0	1	0.00
V2	rom_e2e_shutdown_output	rom_e2e_shutdown_output	10.079s		0	1	0.00
V2	rom_e2e_shutdown_exception_c	rom_e2e_shutdown_exception_c	11.026s		0	1	0.00
V2	rom_e2e_boot_policy_valid	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	11.078s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_dev	10.080s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod	10.093s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod_end	11.098s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_rma	11.110s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	11.114s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_dev	11.115s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod	11.069s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	11.068s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_rma	11.064s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	11.060s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_dev	11.065s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod	11.075s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	11.073s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_rma	10.072s		0	1	0.00
V2	rom_e2e_sigverify_always	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	11.079s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_dev	14.086s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod	14.083s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod_end	13.074s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_rma	13.071s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	10.063s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_dev	10.082s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod	10.081s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	11.083s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_rma	15.091s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	11.071s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_dev	11.069s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod	11.067s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	11.065s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_rma	12.088s		0	1	0.00
V2	rom_e2e_asm_init	rom_e2e_asm_init_test_unlocked0	11.057s		0	1	0.00
		rom_e2e_asm_init_dev	11.055s		0	1	0.00
		rom_e2e_asm_init_prod	11.077s		0	1	0.00
		rom_e2e_asm_init_prod_end	11.077s		0	1	0.00
		rom_e2e_asm_init_rma	10.075s		0	1	0.00
V2	rom_e2e_keymgr_init	rom_e2e_keymgr_init_rom_ext_meas	10.072s		0	1	0.00
		rom_e2e_keymgr_init_rom_ext_no_meas	10.081s		0	1	0.00
		rom_e2e_keymgr_init_rom_ext_invalid_meas	10.082s		0	1	0.00
V2	rom_e2e_static_critical	rom_e2e_static_critical	10.054s		0	1	0.00
V2		TOTAL			43	211	20.38
V2S	chip_sw_aes_masking_off	chip_sw_aes_masking_off	13.020s		0	1	0.00
V2S	chip_sw_rv_core_ibex_lockstep_glitch	chip_sw_rv_core_ibex_lockstep_glitch	3.424m	3.933ms	1	1	100.00
V2S		TOTAL			1	2	50.00
V3	chip_rv_dm_perform_debug	rom_e2e_jtag_debug_test_unlocked0	10.075s		0	1	0.00
		rom_e2e_jtag_debug_dev	11.076s		0	1	0.00
		rom_e2e_jtag_debug_rma	11.093s		0	1	0.00
V3	chip_sw_rv_dm_access_after_hw_reset	chip_sw_rv_dm_access_after_escalation_reset	11.032s		0	1	0.00
V3	chip_sw_plic_alerts	chip_sw_all_escalation_resets	17.488m	13.181ms	1	1	100.00
V3	chip_sw_otp_ctrl_vendor_test_csr_access	chip_sw_otp_ctrl_vendor_test_csr_access	10.028s		0	1	0.00
V3	chip_sw_otp_ctrl_escalation	chip_sw_otp_ctrl_escalation	15.073m	13.189ms	1	1	100.00
V3	chip_sw_coremark	chip_sw_coremark	10.039s		0	1	0.00
V3	chip_sw_power_max_load	chip_sw_power_virus	11.016s		0	1	0.00
V3	rom_e2e_debug	rom_e2e_jtag_debug_test_unlocked0	10.075s		0	1	0.00
		rom_e2e_jtag_debug_dev	11.076s		0	1	0.00
		rom_e2e_jtag_debug_rma	11.093s		0	1	0.00
V3	rom_e2e_jtag_inject	rom_e2e_jtag_inject_test_unlocked0	10.062s		0	1	0.00
		rom_e2e_jtag_inject_dev	10.059s		0	1	0.00
		rom_e2e_jtag_inject_rma	10.056s		0	1	0.00
V3	rom_e2e_self_hash	rom_e2e_self_hash	12.090s		0	1	0.00
V3		TOTAL			1	12	8.33
	Unmapped tests	chip_sw_rstmgr_rst_cnsty_escalation	18.562m	13.182ms	1	1	100.00
		chip_sw_dma_inline_hashing	3.950m	4.433ms	1	1	100.00
		chip_sw_dma_abort	3.694m	4.219ms	0	1	0.00
		rom_e2e_sigverify_mod_exp_test_unlocked0_otbn	10.083s		0	1	0.00
		rom_e2e_sigverify_mod_exp_test_unlocked0_sw	10.081s		0	1	0.00
		rom_e2e_sigverify_mod_exp_dev_otbn	10.084s		0	1	0.00
		rom_e2e_sigverify_mod_exp_dev_sw	10.080s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_otbn	10.076s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_sw	10.072s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_end_otbn	10.068s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_end_sw	10.077s		0	1	0.00
		rom_e2e_sigverify_mod_exp_rma_otbn	11.091s		0	1	0.00
		rom_e2e_sigverify_mod_exp_rma_sw	10.083s		0	1	0.00
		chip_sw_mbx_smoketest	3.706m	4.346ms	1	1	100.00
		TOTAL			52	254	20.47

Failure Buckets

Job returned non-zero exit code has 173 failures:

Test chip_sw_example_rom has 1 failures.

0.chip_sw_example_rom.1
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_example_rom/latest/run.log

  Target //sw/device/tests:example_test_from_rom_sim_dv failed to build
  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests:example_test_from_rom_sim_dv' failed; build aborted: Target //sw/device/tests:example_test_from_rom_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests:example_test_from_rom_sim_dv (cd133b)
      //hw/top_earlgrey/sw/autogen:top_earlgrey (08910b)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 72.056s, Critical Path: 0.07s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_example_manufacturer has 1 failures.

0.chip_sw_example_manufacturer.1
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_example_manufacturer/latest/run.log

  Analyzing: target @@+hooks+manufacturer_test_hooks//:example_test_sim_dv (1 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '@@+hooks+manufacturer_test_hooks//:example_test_sim_dv' failed; build aborted: Target @@+hooks+manufacturer_test_hooks//:example_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      @@+hooks+manufacturer_test_hooks//:example_test_sim_dv (cd133b)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 70.727s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_data_integrity_escalation has 1 failures.

0.chip_sw_data_integrity_escalation.1
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_data_integrity_escalation/latest/run.log

  Analyzing: target //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv (1 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv (cd133b)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 61.928s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_sleep_pin_wake has 1 failures.

0.chip_sw_sleep_pin_wake.1
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_sleep_pin_wake/latest/run.log

  Computing main repo mapping:
  Loading:
  Loading: 0 packages loaded
  WARNING: Target pattern parsing failed.
  ERROR: Skipping '//sw/device/tests/sim_dv:sleep_pin_wake_test_sim_dv': no such target '//sw/device/tests/sim_dv:sleep_pin_wake_test_sim_dv': target 'sleep_pin_wake_test_sim_dv' not declared in package 'sw/device/tests/sim_dv' defined by /nightly/runs/opentitan/sw/device/tests/sim_dv/BUILD
  ERROR: no such target '//sw/device/tests/sim_dv:sleep_pin_wake_test_sim_dv': target 'sleep_pin_wake_test_sim_dv' not declared in package 'sw/device/tests/sim_dv' defined by /nightly/runs/opentitan/sw/device/tests/sim_dv/BUILD
  INFO: Elapsed time: 66.039s
  INFO: 0 processes.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_sleep_pin_retention has 1 failures.

0.chip_sw_sleep_pin_retention.1
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_sleep_pin_retention/latest/run.log

  Computing main repo mapping:
  Loading:
  Loading: 0 packages loaded
  WARNING: Target pattern parsing failed.
  ERROR: Skipping '//sw/device/tests/sim_dv:sleep_pin_retention_test_sim_dv': no such target '//sw/device/tests/sim_dv:sleep_pin_retention_test_sim_dv': target 'sleep_pin_retention_test_sim_dv' not declared in package 'sw/device/tests/sim_dv' defined by /nightly/runs/opentitan/sw/device/tests/sim_dv/BUILD
  ERROR: no such target '//sw/device/tests/sim_dv:sleep_pin_retention_test_sim_dv': target 'sleep_pin_retention_test_sim_dv' not declared in package 'sw/device/tests/sim_dv' defined by /nightly/runs/opentitan/sw/device/tests/sim_dv/BUILD
  INFO: Elapsed time: 52.125s
  INFO: 0 processes.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

... and 168 more tests.

UVM_FATAL @ * us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat" has 8 failures:

Test chip_sw_aes_enc_jitter_en has 1 failures.

0.chip_sw_aes_enc_jitter_en.1
Line 435, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aes_enc_jitter_en/latest/run.log

  UVM_FATAL @  10.200001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_hmac_enc_jitter_en has 1 failures.

0.chip_sw_hmac_enc_jitter_en.1
Line 421, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_hmac_enc_jitter_en/latest/run.log

  UVM_FATAL @  10.200001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_keymgr_dpe_key_derivation_jitter_en has 1 failures.

0.chip_sw_keymgr_dpe_key_derivation_jitter_en.1
Line 414, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation_jitter_en/latest/run.log

  UVM_FATAL @  10.200001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_kmac_mode_kmac_jitter_en has 1 failures.

0.chip_sw_kmac_mode_kmac_jitter_en.1
Line 418, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_kmac_mode_kmac_jitter_en/latest/run.log

  UVM_FATAL @  10.200001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_aes_enc_jitter_en_reduced_freq has 1 failures.

0.chip_sw_aes_enc_jitter_en_reduced_freq.1
Line 416, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aes_enc_jitter_en_reduced_freq/latest/run.log

  UVM_FATAL @  10.200001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more tests.

UVM_ERROR @ * us: (chip_sw_base_vseq.sv:374) virtual_sequencer [chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInBootRom, TIMEOUT = * ns has 5 failures:

Test chip_sw_rstmgr_sw_req has 1 failures.

0.chip_sw_rstmgr_sw_req.1
Line 422, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rstmgr_sw_req/latest/run.log

  UVM_ERROR @ 12026.586846 us: (chip_sw_base_vseq.sv:374) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInBootRom, TIMEOUT = 12000000 ns

  UVM_INFO @ 12026.586846 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_rstmgr_cpu_info has 1 failures.

0.chip_sw_rstmgr_cpu_info.1
Line 421, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rstmgr_cpu_info/latest/run.log

  UVM_ERROR @ 20026.586846 us: (chip_sw_base_vseq.sv:374) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInBootRom, TIMEOUT = 20000000 ns

  UVM_INFO @ 20026.586846 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_aes_entropy has 1 failures.

0.chip_sw_aes_entropy.1
Line 418, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aes_entropy/latest/run.log

  UVM_ERROR @ 15026.586846 us: (chip_sw_base_vseq.sv:374) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInBootRom, TIMEOUT = 15000000 ns

  UVM_INFO @ 15026.586846 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_kmac_mode_cshake has 1 failures.

0.chip_sw_kmac_mode_cshake.1
Line 417, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_kmac_mode_cshake/latest/run.log

  UVM_ERROR @ 12026.586846 us: (chip_sw_base_vseq.sv:374) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInBootRom, TIMEOUT = 12000000 ns

  UVM_INFO @ 12026.586846 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_kmac_mode_kmac has 1 failures.

0.chip_sw_kmac_mode_kmac.1
Line 416, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_kmac_mode_kmac/latest/run.log

  UVM_ERROR @ 12026.586846 us: (chip_sw_base_vseq.sv:374) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInBootRom, TIMEOUT = 12000000 ns

  UVM_INFO @ 12026.586846 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:489) [chip_sw_keymgr_dpe_key_derivation_vseq] Check failed keymgr_pkg::KeyWidth'(get_kmac_digest(kmac_key, data_arr)) == act_digest (* [*] vs * [*]) has 2 failures:

Test chip_sw_keymgr_dpe_key_derivation has 1 failures.

0.chip_sw_keymgr_dpe_key_derivation.1
Line 467, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation/latest/run.log

  UVM_ERROR @ 6500.998888 us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:489) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_dpe_key_derivation_vseq] Check failed keymgr_pkg::KeyWidth'(get_kmac_digest(kmac_key, data_arr)) == act_digest (35842467481214380518335411276204573806028550207660166814059967771080827800830 [0x4f3e1e205f1050694920d9a1ef222e48284f4521b1cba55d0c02e4ff636f0cfe] vs 106217152289308652134023330035928032797740833618967979110430642603755171179141 [0xead4c719ccd0d895ba0de03f4a4bae27fe92d5139f4eedd09d6dca164c076a85])
  UVM_INFO @ 6500.998888 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_keymgr_dpe_key_derivation_prod has 1 failures.

0.chip_sw_keymgr_dpe_key_derivation_prod.1
Line 467, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation_prod/latest/run.log

  UVM_ERROR @ 6500.998888 us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:489) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_dpe_key_derivation_vseq] Check failed keymgr_pkg::KeyWidth'(get_kmac_digest(kmac_key, data_arr)) == act_digest (65037389824968668750297956965749252603657924692343630004884137732330987310609 [0x8fc9dbafa261070ee313afb504a06335e1ad92e68b6201d2107c4d8ad465ce11] vs 21616952410948402469594320362336684688009905973103048433991792115094261290945 [0x2fcac2f06b06b2fe319e2b0aaa00d9db093de8ce6e3926ce23abb3ec8f6757c1])
  UVM_INFO @ 6500.998888 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:521) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@46334) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 2 failures:

Test chip_jtag_csr_rw has 1 failures.

0.chip_jtag_csr_rw.1
Line 6150, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_jtag_csr_rw/latest/run.log

  UVM_ERROR @ 3683.408174 us: (cip_base_scoreboard.sv:521) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@46334) { a_addr: 'h30480000  a_data: 'h1f135537  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h2b  a_opcode: 'h1  a_user: 'h248d9  d_param: 'h0  d_source: 'h2b  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_source_is_overridden: 'h0  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 1, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 3683.408174 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_jtag_mem_access has 1 failures.

0.chip_jtag_mem_access.1
Line 6150, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_jtag_mem_access/latest/run.log

  UVM_ERROR @ 3683.408174 us: (cip_base_scoreboard.sv:521) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@46334) { a_addr: 'h30480000  a_data: 'h1f135537  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h2b  a_opcode: 'h1  a_user: 'h248d9  d_param: 'h0  d_source: 'h2b  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_source_is_overridden: 'h0  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 1, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 3683.408174 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:521) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_soc_mbx_reg_block, TL item: req: (cip_tl_seq_item@1736415) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_csr_aliasing has 1 failures.

0.chip_csr_aliasing.1
Line 265, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_csr_aliasing/latest/run.log

  UVM_ERROR @ 11902.574216 us: (cip_base_scoreboard.sv:521) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface chip_soc_mbx_reg_block, TL item: req: (cip_tl_seq_item@1736415) { a_addr: 'h1465418  a_data: 'h1d3370b2  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h59  a_opcode: 'h1  a_user: 'h26ecd  d_param: 'h0  d_source: 'h59  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h1  d_sink: 'h0  d_user: 'h1f2a  a_source_is_overridden: 'h0  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 11902.574216 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_vseq.sv:293) [chip_common_vseq] Check failed masked_data == exp_data (* [*] vs * [*]) addr * read out mismatch has 1 failures:
- Test chip_same_csr_outstanding has 1 failures.
  - 0.chip_same_csr_outstanding.1
    Line 265, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_same_csr_outstanding/latest/run.log
```
  UVM_ERROR @ 4883.314216 us: (cip_base_vseq.sv:293) [uvm_test_top.env.virtual_sequencer.chip_common_vseq] Check failed masked_data == exp_data (99 [0x63] vs 0 [0x0]) addr 0x30170010 read out mismatch
  UVM_INFO @ 4883.314216 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty has 1 failures:
- Test chip_sw_spi_device_pass_through_collision has 1 failures.
  - 0.chip_sw_spi_device_pass_through_collision.1
    Line 436, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_spi_device_pass_through_collision/latest/run.log
```
  UVM_ERROR @ 4183.631448 us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty
  UVM_INFO @ 4183.631448 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (sw_logger_if.sv:527) [rstmgr_alert_info_test_sim_dv(sw/device/tests/rstmgr_alert_info_test.c:859)] unexpected reset info * has 1 failures:
- Test chip_sw_rstmgr_alert_info has 1 failures.
  - 0.chip_sw_rstmgr_alert_info.1
    Line 430, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rstmgr_alert_info/latest/run.log
```
  UVM_FATAL @ 6530.865576 us: (sw_logger_if.sv:527) [rstmgr_alert_info_test_sim_dv(sw/device/tests/rstmgr_alert_info_test.c:859)] unexpected reset info 20
  UVM_INFO @ 6530.865576 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [rv_core_ibex_nmi_irq_test_sim_dv(sw/device/tests/rv_core_ibex_nmi_irq_test.c:172)] CHECK-fail: Timed out after * usec (* CPU cycles) waiting for nmi_fired has 1 failures:
- Test chip_sw_rv_core_ibex_nmi_irq has 1 failures.
  - 0.chip_sw_rv_core_ibex_nmi_irq.1
    Line 437, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rv_core_ibex_nmi_irq/latest/run.log
```
  UVM_ERROR @ 5103.121448 us: (sw_logger_if.sv:526) [rv_core_ibex_nmi_irq_test_sim_dv(sw/device/tests/rv_core_ibex_nmi_irq_test.c:172)] CHECK-fail: Timed out after 1000 usec (100000 CPU cycles) waiting for nmi_fired
  UVM_INFO @ 5103.121448 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[RamCtn0]] file kmac_app_rom_test_sim_dv.*.vmem could not be opened for r mode has 1 failures:
- Test chip_sw_kmac_app_rom has 1 failures.
  - 0.chip_sw_kmac_app_rom.1
    Line 429, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_kmac_app_rom/latest/run.log
```
  UVM_FATAL @  10.200001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[RamCtn0]] file kmac_app_rom_test_sim_dv.32.vmem could not be opened for r mode
  UVM_INFO @  10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:521) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_soc_mbx_reg_block, TL item: req: (cip_tl_seq_item@36125) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_tl_errors has 1 failures.

0.chip_tl_errors.1
Line 265, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_tl_errors/latest/run.log

  UVM_ERROR @ 3702.854216 us: (cip_base_scoreboard.sv:521) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_soc_mbx_reg_block, TL item: req: (cip_tl_seq_item@36125) { a_addr: 'h1465010  a_data: 'h449e8a6b  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h91  a_opcode: 'h4  a_user: 'h24217  d_param: 'h0  d_source: 'h91  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_source_is_overridden: 'h0  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 1, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 3702.854216 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Error-[CNST-CIF] Constraints inconsistency failure has 1 failures:
- Test chip_padctrl_attributes has 1 failures.
  - 0.chip_padctrl_attributes.1
    Line 312, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_padctrl_attributes/latest/run.log
```
  Error-[CNST-CIF] Constraints inconsistency failure
  ../src/lowrisc_dv_dv_lib_0/dv_base_test.sv, 95
    Constraints are inconsistent and cannot be solved.
    Please check the inconsistent constraints being printed above and rewrite
    them.
```

UVM_FATAL @ * us: sequencer [sequencer] Item_done() called with no outstanding requests. Each call to item_done() must be paired with a previous call to get_next_item(). has 1 failures:

Test chip_sw_dma_abort has 1 failures.

0.chip_sw_dma_abort.1
Line 428, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_dma_abort/latest/run.log

  UVM_FATAL @ 4218.532136 us: uvm_test_top.env.m_spi_device_agents0.sequencer [uvm_test_top.env.m_spi_device_agents0.sequencer] Item_done() called with no outstanding requests. Each call to item_done() must be paired with a previous call to get_next_item().
  UVM_INFO @ 4218.532136 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: chip_soc_dbg_reg_block.soc_dbg_ctrl_jtag.jtag_trace_debug_policy_category reset value: * has 1 failures:
- Test chip_csr_hw_reset has 1 failures.
  - 0.chip_csr_hw_reset.1
    Line 285, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_csr_hw_reset/latest/run.log
```
  UVM_ERROR @ 6408.521130 us: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (99 [0x63] vs 0 [0x0]) Regname: chip_soc_dbg_reg_block.soc_dbg_ctrl_jtag.jtag_trace_debug_policy_category reset value: 0x0
  UVM_INFO @ 6408.521130 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: chip_soc_dbg_reg_block.soc_dbg_ctrl_jtag.jtag_boot_status.boot_greenlight_done reset value: * has 1 failures:
- Test chip_csr_rw has 1 failures.
  - 0.chip_csr_rw.1
    Line 265, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_csr_rw/latest/run.log
```
  UVM_ERROR @ 3806.234216 us: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (7 [0x7] vs 0 [0x0]) Regname: chip_soc_dbg_reg_block.soc_dbg_ctrl_jtag.jtag_boot_status.boot_greenlight_done reset value: 0x0
  UVM_INFO @ 3806.234216 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Offending '(tl_h_i[*].a_source[(IDW - *)-:STIDW] == '0)' has 1 failures:
- Test chip_csr_mem_rw_with_rand_reset has 1 failures.
  - 0.chip_csr_mem_rw_with_rand_reset.1
    Line 271, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_csr_mem_rw_with_rand_reset/latest/run.log
```
      Offending '(tl_h_i[0].a_source[(IDW - 1)-:STIDW] == '0)'
  UVM_ERROR @ 3702.454216 us: (tlul_socket_m1.sv:101) [ASSERT FAILED] idInRange
  UVM_INFO @ 3702.454216 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```