RV_TIMER Simulation Results

Friday March 28 2025 17:03:27 UTC

GitHub Revision: ad05932fb8

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	random	rv_timer_random	1.991m	345.317ms	1	1	100.00
V1	csr_hw_reset	rv_timer_csr_hw_reset	1.370s	50.119us	1	1	100.00
V1	csr_rw	rv_timer_csr_rw	1.450s	44.994us	1	1	100.00
V1	csr_bit_bash	rv_timer_csr_bit_bash	2.660s	767.166us	1	1	100.00
V1	csr_aliasing	rv_timer_csr_aliasing	1.510s	95.952us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	rv_timer_csr_mem_rw_with_rand_reset	1.570s	70.327us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rv_timer_csr_rw	1.450s	44.994us	1	1	100.00
		rv_timer_csr_aliasing	1.510s	95.952us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	random_reset	rv_timer_random_reset	1.450s	38.869us	1	1	100.00
V2	disabled	rv_timer_disabled	1.373m	320.831ms	1	1	100.00
V2	cfg_update_on_fly	rv_timer_cfg_update_on_fly	7.330s	17.912ms	1	1	100.00
V2	no_interrupt_test	rv_timer_cfg_update_on_fly	7.330s	17.912ms	1	1	100.00
V2	stress	rv_timer_stress_all	8.987m	1.432s	1	1	100.00
V2	intr_test	rv_timer_intr_test	1.470s	40.660us	1	1	100.00
V2	tl_d_oob_addr_access	rv_timer_tl_errors	2.500s	424.205us	1	1	100.00
V2	tl_d_illegal_access	rv_timer_tl_errors	2.500s	424.205us	1	1	100.00
V2	tl_d_outstanding_access	rv_timer_csr_hw_reset	1.370s	50.119us	1	1	100.00
		rv_timer_csr_rw	1.450s	44.994us	1	1	100.00
		rv_timer_csr_aliasing	1.510s	95.952us	1	1	100.00
		rv_timer_same_csr_outstanding	1.610s	91.494us	1	1	100.00
V2	tl_d_partial_access	rv_timer_csr_hw_reset	1.370s	50.119us	1	1	100.00
		rv_timer_csr_rw	1.450s	44.994us	1	1	100.00
		rv_timer_csr_aliasing	1.510s	95.952us	1	1	100.00
		rv_timer_same_csr_outstanding	1.610s	91.494us	1	1	100.00
V2		TOTAL			7	7	100.00
V2S	tl_intg_err	rv_timer_sec_cm	1.630s	254.662us	1	1	100.00
		rv_timer_tl_intg_err	1.810s	302.537us	1	1	100.00
V2S	sec_cm_bus_integrity	rv_timer_tl_intg_err	1.810s	302.537us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	rv_timer_stress_all_with_rand_reset	25.920s	17.625ms	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			15	16	93.75

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:890) [rv_timer_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
  • Test rv_timer_stress_all_with_rand_reset has 1 failures.

    • 0.rv_timer_stress_all_with_rand_reset.1
      Line 154, in log /nightly/runs/scratch/master/rv_timer-sim-vcs/0.rv_timer_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 17625051054 ps: (cip_base_vseq.sv:890) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 17625051054 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---