UART Simulation Results

Saturday March 29 2025 17:08:31 UTC

GitHub Revision: 056762e2b4

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	1.950s	554.831us	1	1	100.00
V1	csr_hw_reset	uart_csr_hw_reset	1.580s	60.744us	1	1	100.00
V1	csr_rw	uart_csr_rw	1.440s	49.994us	1	1	100.00
V1	csr_bit_bash	uart_csr_bit_bash	2.540s	704.291us	1	1	100.00
V1	csr_aliasing	uart_csr_aliasing	1.640s	96.494us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	1.620s	111.953us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	1.440s	49.994us	1	1	100.00
		uart_csr_aliasing	1.640s	96.494us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	base_random_seq	uart_tx_rx	19.910s	45.094ms	1	1	100.00
V2	parity	uart_smoke	1.950s	554.831us	1	1	100.00
		uart_tx_rx	19.910s	45.094ms	1	1	100.00
V2	parity_error	uart_intr	5.140s	14.778ms	1	1	100.00
		uart_rx_parity_err	13.330s	38.503ms	1	1	100.00
V2	watermark	uart_tx_rx	19.910s	45.094ms	1	1	100.00
		uart_intr	5.140s	14.778ms	1	1	100.00
V2	fifo_full	uart_fifo_full	1.965m	187.924ms	1	1	100.00
V2	fifo_overflow	uart_fifo_overflow	7.720s	24.375ms	1	1	100.00
V2	fifo_reset	uart_fifo_reset	15.900s	38.146ms	1	1	100.00
V2	rx_frame_err	uart_intr	5.140s	14.778ms	1	1	100.00
V2	rx_break_err	uart_intr	5.140s	14.778ms	1	1	100.00
V2	rx_timeout	uart_intr	5.140s	14.778ms	1	1	100.00
V2	perf	uart_perf	2.002m	13.662ms	1	1	100.00
V2	sys_loopback	uart_loopback	6.820s	5.722ms	1	1	100.00
V2	line_loopback	uart_loopback	6.820s	5.722ms	1	1	100.00
V2	rx_noise_filter	uart_noise_filter	53.590s	156.430ms	1	1	100.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	2.300s	3.653ms	1	1	100.00
V2	tx_overide	uart_tx_ovrd	2.630s	2.731ms	1	1	100.00
V2	rx_oversample	uart_rx_oversample	8.570s	5.226ms	1	1	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	2.840m	99.004ms	1	1	100.00
V2	stress_all	uart_stress_all	7.231m	579.858ms	1	1	100.00
V2	alert_test	uart_alert_test	1.300s	49.077us	1	1	100.00
V2	intr_test	uart_intr_test	1.430s	47.702us	1	1	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	2.540s	442.914us	1	1	100.00
V2	tl_d_illegal_access	uart_tl_errors	2.540s	442.914us	1	1	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	1.580s	60.744us	1	1	100.00
		uart_csr_rw	1.440s	49.994us	1	1	100.00
		uart_csr_aliasing	1.640s	96.494us	1	1	100.00
		uart_same_csr_outstanding	1.450s	84.702us	1	1	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	1.580s	60.744us	1	1	100.00
		uart_csr_rw	1.440s	49.994us	1	1	100.00
		uart_csr_aliasing	1.640s	96.494us	1	1	100.00
		uart_same_csr_outstanding	1.450s	84.702us	1	1	100.00
V2		TOTAL			18	18	100.00
V2S	tl_intg_err	uart_sec_cm	1.620s	252.120us	1	1	100.00
		uart_tl_intg_err	2.040s	335.413us	1	1	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	2.040s	335.413us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	12.180s	5.176ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			27	27	100.00