KEYMGR_DPE Simulation Results

Monday March 31 2025 17:01:40 UTC

GitHub Revision: 1eaf8e5dc0

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	keymgr_dpe_smoke	10.940s	1.652ms	1	1	100.00
V1	csr_hw_reset	keymgr_dpe_csr_hw_reset	1.640s	57.786us	1	1	100.00
V1	csr_rw	keymgr_dpe_csr_rw	1.740s	52.785us	1	1	100.00
V1	csr_bit_bash	keymgr_dpe_csr_bit_bash	6.740s	1.209ms	1	1	100.00
V1	csr_aliasing	keymgr_dpe_csr_aliasing	4.260s	469.122us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	keymgr_dpe_csr_mem_rw_with_rand_reset	1.780s	85.411us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	keymgr_dpe_csr_rw	1.740s	52.785us	1	1	100.00
		keymgr_dpe_csr_aliasing	4.260s	469.122us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	intr_test	keymgr_dpe_intr_test	1.390s	30.535us	1	1	100.00
V2	alert_test	keymgr_dpe_alert_test	1.530s	40.410us	1	1	100.00
V2	tl_d_oob_addr_access	keymgr_dpe_tl_errors	2.790s	246.662us	1	1	100.00
V2	tl_d_illegal_access	keymgr_dpe_tl_errors	2.790s	246.662us	1	1	100.00
V2	tl_d_outstanding_access	keymgr_dpe_csr_hw_reset	1.640s	57.786us	1	1	100.00
		keymgr_dpe_csr_rw	1.740s	52.785us	1	1	100.00
		keymgr_dpe_csr_aliasing	4.260s	469.122us	1	1	100.00
		keymgr_dpe_same_csr_outstanding	2.210s	162.370us	1	1	100.00
V2	tl_d_partial_access	keymgr_dpe_csr_hw_reset	1.640s	57.786us	1	1	100.00
		keymgr_dpe_csr_rw	1.740s	52.785us	1	1	100.00
		keymgr_dpe_csr_aliasing	4.260s	469.122us	1	1	100.00
		keymgr_dpe_same_csr_outstanding	2.210s	162.370us	1	1	100.00
V2		TOTAL			4	4	100.00
V2S	tl_intg_err	keymgr_dpe_sec_cm	7.090s	1.141ms	1	1	100.00
		keymgr_dpe_tl_intg_err	3.510s	365.705us	1	1	100.00
V2S	shadow_reg_update_error	keymgr_dpe_shadow_reg_errors	1.510s	9.848us	0	1	0.00
V2S	shadow_reg_read_clear_staged_value	keymgr_dpe_shadow_reg_errors	1.510s	9.848us	0	1	0.00
V2S	shadow_reg_storage_error	keymgr_dpe_shadow_reg_errors	1.510s	9.848us	0	1	0.00
V2S	shadowed_reset_glitch	keymgr_dpe_shadow_reg_errors	1.510s	9.848us	0	1	0.00
V2S	shadow_reg_update_error_with_csr_rw	keymgr_dpe_shadow_reg_errors_with_csr_rw	1.870s	44.015us	0	1	0.00
V2S	prim_count_check	keymgr_dpe_sec_cm	7.090s	1.141ms	1	1	100.00
V2S	prim_fsm_check	keymgr_dpe_sec_cm	7.090s	1.141ms	1	1	100.00
V2S		TOTAL			2	4	50.00
		TOTAL			12	14	85.71

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:986) [keymgr_dpe_common_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == * (* [*] vs * [*]) fatal error fatal_fault_err does not trigger! has 2 failures:

  • Test keymgr_dpe_shadow_reg_errors has 1 failures.

    • 0.keymgr_dpe_shadow_reg_errors.1
      Line 75, in log /nightly/runs/scratch/master/keymgr_dpe-sim-vcs/0.keymgr_dpe_shadow_reg_errors/latest/run.log

        UVM_ERROR @   9847633 ps: (cip_base_vseq.sv:986) [uvm_test_top.env.virtual_sequencer.keymgr_dpe_common_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == 1 (0 [0x0] vs 1 [0x1]) fatal error fatal_fault_err does not trigger!
        UVM_INFO @   9847633 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test keymgr_dpe_shadow_reg_errors_with_csr_rw has 1 failures.

    • 0.keymgr_dpe_shadow_reg_errors_with_csr_rw.1
      Line 75, in log /nightly/runs/scratch/master/keymgr_dpe-sim-vcs/0.keymgr_dpe_shadow_reg_errors_with_csr_rw/latest/run.log

        UVM_ERROR @  44014573 ps: (cip_base_vseq.sv:986) [uvm_test_top.env.virtual_sequencer.keymgr_dpe_common_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == 1 (0 [0x0] vs 1 [0x1]) fatal error fatal_fault_err does not trigger!
        UVM_INFO @  44014573 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---