UART Simulation Results

Monday March 31 2025 17:01:40 UTC

GitHub Revision: 1eaf8e5dc0

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	2.230s	554.956us	1	1	100.00
V1	csr_hw_reset	uart_csr_hw_reset	1.470s	60.911us	1	1	100.00
V1	csr_rw	uart_csr_rw	1.480s	50.160us	1	1	100.00
V1	csr_bit_bash	uart_csr_bit_bash	2.540s	696.041us	1	1	100.00
V1	csr_aliasing	uart_csr_aliasing	1.480s	96.452us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	1.640s	112.953us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	1.480s	50.160us	1	1	100.00
		uart_csr_aliasing	1.480s	96.452us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	base_random_seq	uart_tx_rx	19.680s	45.094ms	1	1	100.00
V2	parity	uart_smoke	2.230s	554.956us	1	1	100.00
		uart_tx_rx	19.680s	45.094ms	1	1	100.00
V2	parity_error	uart_intr	4.880s	14.777ms	1	1	100.00
		uart_rx_parity_err	13.180s	38.503ms	1	1	100.00
V2	watermark	uart_tx_rx	19.680s	45.094ms	1	1	100.00
		uart_intr	4.880s	14.777ms	1	1	100.00
V2	fifo_full	uart_fifo_full	1.936m	187.925ms	1	1	100.00
V2	fifo_overflow	uart_fifo_overflow	7.660s	24.375ms	1	1	100.00
V2	fifo_reset	uart_fifo_reset	15.540s	38.146ms	1	1	100.00
V2	rx_frame_err	uart_intr	4.880s	14.777ms	1	1	100.00
V2	rx_break_err	uart_intr	4.880s	14.777ms	1	1	100.00
V2	rx_timeout	uart_intr	4.880s	14.777ms	1	1	100.00
V2	perf	uart_perf	1.990m	13.661ms	1	1	100.00
V2	sys_loopback	uart_loopback	6.630s	5.722ms	1	1	100.00
V2	line_loopback	uart_loopback	6.630s	5.722ms	1	1	100.00
V2	rx_noise_filter	uart_noise_filter	52.940s	156.430ms	1	1	100.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	2.240s	3.654ms	1	1	100.00
V2	tx_overide	uart_tx_ovrd	2.480s	2.731ms	1	1	100.00
V2	rx_oversample	uart_rx_oversample	8.490s	5.225ms	1	1	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	1.851m	97.795ms	1	1	100.00
V2	stress_all	uart_stress_all	7.374m	626.402ms	1	1	100.00
V2	alert_test	uart_alert_test	1.460s	49.952us	1	1	100.00
V2	intr_test	uart_intr_test	1.350s	47.827us	1	1	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	2.530s	442.164us	1	1	100.00
V2	tl_d_illegal_access	uart_tl_errors	2.530s	442.164us	1	1	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	1.470s	60.911us	1	1	100.00
		uart_csr_rw	1.480s	50.160us	1	1	100.00
		uart_csr_aliasing	1.480s	96.452us	1	1	100.00
		uart_same_csr_outstanding	1.450s	83.077us	1	1	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	1.470s	60.911us	1	1	100.00
		uart_csr_rw	1.480s	50.160us	1	1	100.00
		uart_csr_aliasing	1.480s	96.452us	1	1	100.00
		uart_same_csr_outstanding	1.450s	83.077us	1	1	100.00
V2		TOTAL			18	18	100.00
V2S	tl_intg_err	uart_sec_cm	1.570s	285.454us	1	1	100.00
		uart_tl_intg_err	2.040s	355.871us	1	1	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	2.040s	355.871us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	11.790s	5.178ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			27	27	100.00