EDN Simulation Results

Tuesday April 01 2025 17:01:25 UTC

GitHub Revision: e5ceec3ceb

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke edn_smoke 1.770s 41.571us 1 1 100.00
V1 csr_hw_reset edn_csr_hw_reset 1.660s 57.051us 1 1 100.00
V1 csr_rw edn_csr_rw 1.660s 44.355us 1 1 100.00
V1 csr_bit_bash edn_csr_bit_bash 3.260s 559.700us 1 1 100.00
V1 csr_aliasing edn_csr_aliasing 1.880s 97.311us 1 1 100.00
V1 csr_mem_rw_with_rand_reset edn_csr_mem_rw_with_rand_reset 1.810s 79.963us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr edn_csr_rw 1.660s 44.355us 1 1 100.00
edn_csr_aliasing 1.880s 97.311us 1 1 100.00
V1 TOTAL 6 6 100.00
V2 firmware edn_genbits 1.810s 49.011us 1 1 100.00
V2 csrng_commands edn_genbits 1.810s 49.011us 1 1 100.00
V2 genbits edn_genbits 1.810s 49.011us 1 1 100.00
V2 interrupts edn_intr 1.630s 29.251us 1 1 100.00
V2 alerts edn_alert 1.770s 73.091us 1 1 100.00
V2 errs edn_err 1.690s 34.571us 1 1 100.00
V2 disable edn_disable 1.720s 28.211us 1 1 100.00
edn_disable_auto_req_mode 1.750s 43.571us 1 1 100.00
V2 stress_all edn_stress_all 4.060s 769.851us 1 1 100.00
V2 intr_test edn_intr_test 1.600s 40.790us 1 1 100.00
V2 alert_test edn_alert_test 1.750s 50.920us 1 1 100.00
V2 tl_d_oob_addr_access edn_tl_errors 2.720s 299.832us 1 1 100.00
V2 tl_d_illegal_access edn_tl_errors 2.720s 299.832us 1 1 100.00
V2 tl_d_outstanding_access edn_csr_hw_reset 1.660s 57.051us 1 1 100.00
edn_csr_rw 1.660s 44.355us 1 1 100.00
edn_csr_aliasing 1.880s 97.311us 1 1 100.00
edn_same_csr_outstanding 1.820s 80.963us 1 1 100.00
V2 tl_d_partial_access edn_csr_hw_reset 1.660s 57.051us 1 1 100.00
edn_csr_rw 1.660s 44.355us 1 1 100.00
edn_csr_aliasing 1.880s 97.311us 1 1 100.00
edn_same_csr_outstanding 1.820s 80.963us 1 1 100.00
V2 TOTAL 11 11 100.00
V2S tl_intg_err edn_sec_cm 4.390s 1.170ms 1 1 100.00
edn_tl_intg_err 2.190s 212.397us 1 1 100.00
V2S sec_cm_config_regwen edn_regwen 1.780s 50.011us 1 1 100.00
V2S sec_cm_config_mubi edn_alert 1.770s 73.091us 1 1 100.00
V2S sec_cm_main_sm_fsm_sparse edn_sec_cm 4.390s 1.170ms 1 1 100.00
V2S sec_cm_ack_sm_fsm_sparse edn_sec_cm 4.390s 1.170ms 1 1 100.00
V2S sec_cm_fifo_ctr_redun edn_sec_cm 4.390s 1.170ms 1 1 100.00
V2S sec_cm_ctr_redun edn_sec_cm 4.390s 1.170ms 1 1 100.00
V2S sec_cm_main_sm_ctr_local_esc edn_alert 1.770s 73.091us 1 1 100.00
edn_sec_cm 4.390s 1.170ms 1 1 100.00
V2S sec_cm_cs_rdata_bus_consistency edn_alert 1.770s 73.091us 1 1 100.00
V2S sec_cm_tile_link_bus_integrity edn_tl_intg_err 2.190s 212.397us 1 1 100.00
V2S TOTAL 3 3 100.00
V3 stress_all_with_rand_reset edn_stress_all_with_rand_reset 0 1 0.00
V3 TOTAL 0 1 0.00
TOTAL 20 21 95.24

Failure Buckets