KMAC/MASKED Simulation Results

Tuesday April 01 2025 17:01:25 UTC

GitHub Revision: e5ceec3ceb

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	53.540s	13.491ms	1	1	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.720s	62.452us	1	1	100.00
V1	csr_rw	kmac_csr_rw	1.630s	69.661us	1	1	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	7.360s	2.015ms	1	1	100.00
V1	csr_aliasing	kmac_csr_aliasing	4.200s	805.208us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.050s	179.411us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.630s	69.661us	1	1	100.00
		kmac_csr_aliasing	4.200s	805.208us	1	1	100.00
V1	mem_walk	kmac_mem_walk	1.710s	37.035us	1	1	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.940s	101.994us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	39.931m	351.557ms	1	1	100.00
V2	burst_write	kmac_burst_write	15.444m	111.402ms	1	1	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	27.348m	259.693ms	1	1	100.00
		kmac_test_vectors_sha3_256	24.707m	239.754ms	1	1	100.00
		kmac_test_vectors_sha3_384	19.514m	182.081ms	1	1	100.00
		kmac_test_vectors_sha3_512	15.102m	132.323ms	1	1	100.00
		kmac_test_vectors_shake_128	2.776m	52.240ms	1	1	100.00
		kmac_test_vectors_shake_256	4.705m	74.645ms	1	1	100.00
		kmac_test_vectors_kmac	2.950s	352.830us	1	1	100.00
		kmac_test_vectors_kmac_xof	2.870s	278.787us	1	1	100.00
V2	sideload	kmac_sideload	5.250m	59.178ms	1	1	100.00
V2	app	kmac_app	3.741m	45.156ms	1	1	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	4.138m	53.130ms	1	1	100.00
V2	entropy_refresh	kmac_entropy_refresh	4.582m	55.968ms	1	1	100.00
V2	error	kmac_error	5.074m	56.288ms	1	1	100.00
V2	key_error	kmac_key_error	7.430s	3.789ms	1	1	100.00
V2	sideload_invalid	kmac_sideload_invalid	3.590s	353.121us	1	1	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	27.860s	5.654ms	1	1	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	1.750s	142.453us	1	1	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	50.250s	20.407ms	1	1	100.00
V2	lc_escalation	kmac_lc_escalation	3.160s	311.308us	0	1	0.00
V2	stress_all	kmac_stress_all	24.383m	254.522ms	1	1	100.00
V2	intr_test	kmac_intr_test	1.570s	32.910us	1	1	100.00
V2	alert_test	kmac_alert_test	1.400s	43.494us	1	1	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	2.310s	226.703us	1	1	100.00
V2	tl_d_illegal_access	kmac_tl_errors	2.310s	226.703us	1	1	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.720s	62.452us	1	1	100.00
		kmac_csr_rw	1.630s	69.661us	1	1	100.00
		kmac_csr_aliasing	4.200s	805.208us	1	1	100.00
		kmac_same_csr_outstanding	1.910s	180.161us	1	1	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.720s	62.452us	1	1	100.00
		kmac_csr_rw	1.630s	69.661us	1	1	100.00
		kmac_csr_aliasing	4.200s	805.208us	1	1	100.00
		kmac_same_csr_outstanding	1.910s	180.161us	1	1	100.00
V2		TOTAL			25	26	96.15
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.620s	14.848us	0	1	0.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.620s	14.848us	0	1	0.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.620s	14.848us	0	1	0.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.620s	14.848us	0	1	0.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	1.860s	83.057us	0	1	0.00
V2S	tl_intg_err	kmac_sec_cm	33.290s	13.148ms	1	1	100.00
		kmac_tl_intg_err	2.920s	396.788us	1	1	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	2.920s	396.788us	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	3.160s	311.308us	0	1	0.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	53.540s	13.491ms	1	1	100.00
V2S	sec_cm_key_sideload	kmac_sideload	5.250m	59.178ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.620s	14.848us	0	1	0.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	33.290s	13.148ms	1	1	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	33.290s	13.148ms	1	1	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	33.290s	13.148ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	53.540s	13.491ms	1	1	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	3.160s	311.308us	0	1	0.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	33.290s	13.148ms	1	1	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	4.160m	47.606ms	1	1	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	53.540s	13.491ms	1	1	100.00
V2S		TOTAL			3	5	60.00
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	4.840s	592.915us	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			36	40	90.00

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:986) [kmac_common_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == * (* [*] vs * [*]) fatal error fatal_fault_err does not trigger! has 2 failures:

  • Test kmac_shadow_reg_errors has 1 failures.

    • 0.kmac_shadow_reg_errors.1
      Line 75, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/0.kmac_shadow_reg_errors/latest/run.log

        UVM_ERROR @  14847673 ps: (cip_base_vseq.sv:986) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == 1 (0 [0x0] vs 1 [0x1]) fatal error fatal_fault_err does not trigger!
        UVM_INFO @  14847673 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test kmac_shadow_reg_errors_with_csr_rw has 1 failures.

    • 0.kmac_shadow_reg_errors_with_csr_rw.1
      Line 75, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/0.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

        UVM_ERROR @  83056552 ps: (cip_base_vseq.sv:986) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == 1 (0 [0x0] vs 1 [0x1]) fatal error fatal_fault_err does not trigger!
        UVM_INFO @  83056552 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:986) [kmac_lc_escalation_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == * (* [*] vs * [*]) fatal error fatal_fault_err does not trigger! has 1 failures:

  • Test kmac_lc_escalation has 1 failures.

    • 0.kmac_lc_escalation.1
      Line 75, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/0.kmac_lc_escalation/latest/run.log

        UVM_ERROR @ 311308378 ps: (cip_base_vseq.sv:986) [uvm_test_top.env.virtual_sequencer.kmac_lc_escalation_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == 1 (0 [0x0] vs 1 [0x1]) fatal error fatal_fault_err does not trigger!
        UVM_INFO @ 311308378 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (kmac_scoreboard.sv:1202) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 1 failures:

  • Test kmac_stress_all_with_rand_reset has 1 failures.

    • 0.kmac_stress_all_with_rand_reset.1
      Line 80, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 592914798 ps: (kmac_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483712 [0x80000040]) reg name: kmac_reg_block.err_code
        UVM_INFO @ 592914798 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---