CHIP Simulation Results

Tuesday April 01 2025 17:01:25 UTC

GitHub Revision: `e5ceec3ceb`

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	chip_sw_uart_tx_rx	chip_sw_uart_tx_rx	55.067s		0	1	0.00
V1	chip_sw_uart_rx_overflow	chip_sw_uart_tx_rx	55.067s		0	1	0.00
V1	chip_sw_uart_rand_baudrate	chip_sw_uart_rand_baudrate	1.071m		0	1	0.00
V1	chip_sw_uart_tx_rx_alt_clk_freq	chip_sw_uart_tx_rx_alt_clk_freq	1.020m		0	1	0.00
		chip_sw_uart_tx_rx_alt_clk_freq_low_speed	1.020m		0	1	0.00
V1	chip_sw_gpio_out	chip_sw_gpio	5.772m	5.102ms	1	1	100.00
V1	chip_sw_gpio_in	chip_sw_gpio	5.772m	5.102ms	1	1	100.00
V1	chip_sw_gpio_irq	chip_sw_gpio	5.772m	5.102ms	1	1	100.00
V1	chip_sw_example_tests	chip_sw_example_rom	1.152m		0	1	0.00
		chip_sw_example_manufacturer	2.139m		0	1	0.00
		chip_sw_example_concurrency	2.122m		0	1	0.00
		chip_sw_uart_smoketest_signed	11.126s		0	1	0.00
V1	csr_bit_bash	chip_csr_bit_bash	9.660s		0	1	0.00
V1	csr_aliasing	chip_csr_aliasing	9.450s		0	1	0.00
V1	regwen_csr_and_corresponding_lockable_csr	chip_csr_aliasing	9.450s		0	1	0.00
V1	xbar_smoke	xbar_smoke	14.890s	49.909us	1	1	100.00
V1		TOTAL			2	12	16.67
V2	chip_sw_spi_device_flash_mode	chip_sw_uart_tx_rx_bootstrap	45.055s		0	1	0.00
V2	chip_sw_spi_device_pass_through	chip_sw_spi_device_pass_through	31.061s		0	1	0.00
V2	chip_sw_spi_device_pass_through_collision	chip_sw_spi_device_pass_through_collision	3.890m	4.172ms	0	1	0.00
V2	chip_sw_spi_device_tpm	chip_sw_spi_device_tpm	41.199s		0	1	0.00
V2	chip_sw_spi_host_tx_rx	chip_sw_spi_host_tx_rx	38.072s		0	1	0.00
V2	chip_sw_i2c_host_tx_rx	chip_sw_i2c_host_tx_rx	1.020m		0	1	0.00
V2	chip_sw_i2c_device_tx_rx	chip_sw_i2c_device_tx_rx	1.020m		0	1	0.00
V2	chip_pin_mux	chip_padctrl_attributes	3.290s		0	1	0.00
V2	chip_padctrl_attributes	chip_padctrl_attributes	3.290s		0	1	0.00
V2	chip_sw_sleep_pin_wake	chip_sw_sleep_pin_wake	2.022m		0	1	0.00
V2	chip_sw_sleep_pin_retention	chip_sw_sleep_pin_retention	1.988m		0	1	0.00
V2	chip_sw_data_integrity	chip_sw_data_integrity_escalation	2.022m		0	1	0.00
V2	chip_sw_instruction_integrity	chip_sw_data_integrity_escalation	2.022m		0	1	0.00
V2	chip_jtag_csr_rw	chip_jtag_csr_rw	2.486m	3.683ms	0	1	0.00
V2	chip_jtag_mem_access	chip_jtag_mem_access	2.268m	3.683ms	0	1	0.00
V2	chip_rv_dm_ndm_reset_req	chip_rv_dm_ndm_reset_req	5.056m	6.359ms	1	1	100.00
V2	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	12.041s		0	1	0.00
V2	chip_rv_dm_access_after_wakeup	chip_sw_rv_dm_access_after_wakeup	11.041s		0	1	0.00
V2	chip_rv_dm_lc_disabled	chip_rv_dm_lc_disabled	10.035m	17.314ms	1	1	100.00
V2	chip_sw_timer	chip_sw_rv_timer_irq	4.868m	5.035ms	1	1	100.00
V2	chip_sw_aon_timer_wakeup_irq	chip_sw_aon_timer_irq	11.035s		0	1	0.00
V2	chip_sw_aon_timer_wdog_bark_irq	chip_sw_aon_timer_irq	11.035s		0	1	0.00
V2	chip_sw_aon_timer_wdog_lc_escalate	chip_sw_aon_timer_wdog_lc_escalate	10.029s		0	1	0.00
V2	chip_sw_aon_timer_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	10.034s		0	1	0.00
V2	chip_sw_aon_timer_sleep_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	10.034s		0	1	0.00
V2	chip_sw_aon_timer_sleep_wdog_sleep_pause	chip_sw_aon_timer_sleep_wdog_sleep_pause	11.039s		0	1	0.00
V2	chip_sw_plic_all_irqs	chip_plic_all_irqs	11.038s		0	1	0.00
V2	chip_sw_plic_sw_irq	chip_sw_plic_sw_irq	3.305m	3.974ms	1	1	100.00
V2	chip_sw_clkmgr_idle_trans	chip_sw_otbn_randomness	4.131m	4.339ms	1	1	100.00
		chip_sw_aes_idle	3.330m	3.983ms	1	1	100.00
		chip_sw_hmac_enc_idle	3.715m	4.121ms	1	1	100.00
		chip_sw_kmac_idle	3.355m	3.960ms	1	1	100.00
V2	chip_sw_clkmgr_off_trans	chip_sw_clkmgr_off_aes_trans	11.025s		0	1	0.00
		chip_sw_clkmgr_off_hmac_trans	11.024s		0	1	0.00
		chip_sw_clkmgr_off_kmac_trans	11.024s		0	1	0.00
		chip_sw_clkmgr_off_otbn_trans	11.024s		0	1	0.00
V2	chip_sw_clkmgr_div	chip_sw_clkmgr_external_clk_src_for_lc	11.078s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	10.097s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	11.097s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	11.070s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	11.067s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	11.061s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	11.056s		0	1	0.00
V2	chip_sw_clkmgr_external_clk_src_for_lc	chip_sw_clkmgr_external_clk_src_for_lc	11.078s		0	1	0.00
V2	chip_sw_clkmgr_external_clk_src_for_sw	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	10.097s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	11.097s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	11.070s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	11.067s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	11.061s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	11.056s		0	1	0.00
V2	chip_sw_clkmgr_jitter	chip_sw_otbn_ecdsa_op_irq_jitter_en	11.025s		0	1	0.00
		chip_sw_aes_enc_jitter_en	43.150s	10.200us	0	1	0.00
		chip_sw_hmac_enc_jitter_en	43.570s	10.200us	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	43.400s	10.200us	0	1	0.00
		chip_sw_kmac_mode_kmac_jitter_en	43.410s	10.200us	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	11.034s		0	1	0.00
		chip_sw_clkmgr_jitter	3.179m	3.929ms	1	1	100.00
V2	chip_sw_clkmgr_extended_range	chip_sw_clkmgr_jitter_reduced_freq	3.196m	4.007ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq	11.015s		0	1	0.00
		chip_sw_aes_enc_jitter_en_reduced_freq	43.470s	10.200us	0	1	0.00
		chip_sw_hmac_enc_jitter_en_reduced_freq	43.360s	10.200us	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en_reduced_freq	43.690s	10.200us	0	1	0.00
		chip_sw_kmac_mode_kmac_jitter_en_reduced_freq	43.800s	10.200us	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq	43.240s	10.200us	0	1	0.00
		chip_sw_csrng_edn_concurrency_reduced_freq	11.020s		0	1	0.00
V2	chip_sw_clkmgr_deep_sleep_frequency	chip_sw_ast_clk_outputs	11.044s		0	1	0.00
V2	chip_sw_clkmgr_sleep_frequency	chip_sw_clkmgr_sleep_frequency	11.053s		0	1	0.00
V2	chip_sw_clkmgr_reset_frequency	chip_sw_clkmgr_reset_frequency	11.061s		0	1	0.00
V2	chip_sw_clkmgr_escalation_reset	chip_sw_all_escalation_resets	37.130s	10.200us	0	1	0.00
V2	chip_sw_pwrmgr_external_full_reset	chip_sw_pwrmgr_full_aon_reset	7.659m	11.326ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_all_reset_reqs	chip_sw_aon_timer_wdog_bite_reset	10.034s		0	1	0.00
V2	chip_sw_pwrmgr_wdog_reset	chip_sw_pwrmgr_wdog_reset	11.036s		0	1	0.00
V2	chip_sw_pwrmgr_aon_power_glitch_reset	chip_sw_pwrmgr_full_aon_reset	7.659m	11.326ms	1	1	100.00
V2	chip_sw_pwrmgr_main_power_glitch_reset	chip_sw_pwrmgr_main_power_glitch_reset	13.045s		0	1	0.00
V2	chip_sw_pwrmgr_random_sleep_power_glitch_reset	chip_sw_pwrmgr_random_sleep_power_glitch_reset	16.053s		0	1	0.00
V2	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	12.024s		0	1	0.00
V2	chip_sw_pwrmgr_sleep_power_glitch_reset	chip_sw_pwrmgr_sleep_power_glitch_reset	15.052s		0	1	0.00
V2	chip_sw_pwrmgr_sleep_disabled	chip_sw_pwrmgr_sleep_disabled	13.047s		0	1	0.00
V2	chip_sw_pwrmgr_escalation_reset	chip_sw_all_escalation_resets	37.130s	10.200us	0	1	0.00
V2	chip_sw_rstmgr_sys_reset_info	chip_rv_dm_ndm_reset_req	5.056m	6.359ms	1	1	100.00
V2	chip_sw_rstmgr_cpu_info	chip_sw_rstmgr_cpu_info	20.914m	20.027ms	0	1	0.00
V2	chip_sw_rstmgr_sw_req_reset	chip_sw_rstmgr_sw_req	6.129m	6.349ms	1	1	100.00
V2	chip_sw_rstmgr_alert_info	chip_sw_rstmgr_alert_info	5.900m	6.516ms	0	1	0.00
V2	chip_sw_rstmgr_sw_rst	chip_sw_rstmgr_sw_rst	3.446m	3.951ms	1	1	100.00
V2	chip_sw_rstmgr_escalation_reset	chip_sw_all_escalation_resets	37.130s	10.200us	0	1	0.00
V2	chip_sw_alert_handler_alerts	chip_sw_alert_test	11.012s		0	1	0.00
V2	chip_sw_alert_handler_escalations	chip_sw_alert_handler_escalation	11.012s		0	1	0.00
V2	chip_sw_all_escalation_resets	chip_sw_all_escalation_resets	37.130s	10.200us	0	1	0.00
V2	chip_sw_alert_handler_irqs	chip_plic_all_irqs	11.038s		0	1	0.00
V2	chip_sw_alert_handler_entropy	chip_sw_alert_handler_entropy	13.044s		0	1	0.00
V2	chip_sw_alert_handler_crashdump	chip_sw_rstmgr_alert_info	5.900m	6.516ms	0	1	0.00
V2	chip_sw_alert_handler_ping_timeout	chip_sw_alert_handler_ping_timeout	11.021s		0	1	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_alerts	chip_sw_alert_handler_lpg_sleep_mode_alerts	11.020s		0	1	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_pings	chip_sw_alert_handler_lpg_sleep_mode_pings	11.028s		0	1	0.00
V2	chip_sw_alert_handler_lpg_clock_off	chip_sw_alert_handler_lpg_clkoff	11.028s		0	1	0.00
V2	chip_sw_alert_handler_lpg_reset_toggle	chip_sw_alert_handler_lpg_reset_toggle	11.025s		0	1	0.00
V2	chip_sw_alert_handler_reverse_ping_in_deep_sleep	chip_sw_alert_handler_reverse_ping_in_deep_sleep	11.018s		0	1	0.00
V2	chip_sw_lc_ctrl_alert_handler_escalation	chip_sw_alert_handler_escalation	11.012s		0	1	0.00
V2	chip_sw_lc_ctrl_jtag_access	chip_sw_lc_ctrl_transition	16.045s		0	1	0.00
V2	chip_sw_lc_ctrl_otp_hw_cfg	chip_sw_lc_ctrl_otp_hw_cfg	37.173s		0	1	0.00
V2	chip_sw_lc_ctrl_init	chip_sw_lc_ctrl_transition	16.045s		0	1	0.00
V2	chip_sw_lc_ctrl_transitions	chip_sw_lc_ctrl_transition	16.045s		0	1	0.00
V2	chip_sw_lc_ctrl_kmac_req	chip_sw_lc_ctrl_transition	16.045s		0	1	0.00
V2	chip_sw_lc_ctrl_key_div	chip_sw_keymgr_dpe_key_derivation_prod	5.820m	6.484ms	0	1	0.00
V2	chip_sw_lc_ctrl_broadcast	chip_sw_otp_ctrl_lc_signals_test_unlocked0	19.092s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_dev	15.067s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_prod	13.047s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_rma	13.044s		0	1	0.00
		chip_sw_lc_ctrl_transition	16.045s		0	1	0.00
		chip_sw_keymgr_dpe_key_derivation	5.891m	6.484ms	0	1	0.00
		chip_sw_rom_ctrl_integrity_check	7.811m	11.330ms	1	1	100.00
		chip_sw_sram_ctrl_execution_main	11.034s		0	1	0.00
		chip_prim_tl_access	8.638m	13.660ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_lc	11.078s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	10.097s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	11.097s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	11.070s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	11.067s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	11.061s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	11.056s		0	1	0.00
		chip_rv_dm_lc_disabled	10.035m	17.314ms	1	1	100.00
V2	chip_sw_aes_enc	chip_sw_aes_enc	3.336m	4.074ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	43.150s	10.200us	0	1	0.00
V2	chip_sw_aes_entropy	chip_sw_aes_entropy	3.264m	3.968ms	1	1	100.00
V2	chip_sw_aes_idle	chip_sw_aes_idle	3.330m	3.983ms	1	1	100.00
V2	chip_sw_hmac_enc	chip_sw_hmac_enc	3.363m	4.074ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	43.570s	10.200us	0	1	0.00
V2	chip_sw_hmac_idle	chip_sw_hmac_enc_idle	3.715m	4.121ms	1	1	100.00
V2	chip_sw_kmac_enc	chip_sw_kmac_mode_cshake	3.193m	3.997ms	1	1	100.00
		chip_sw_kmac_mode_kmac	4.328m	4.245ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	43.410s	10.200us	0	1	0.00
V2	chip_sw_kmac_app_keymgr	chip_sw_keymgr_dpe_key_derivation	5.891m	6.484ms	0	1	0.00
V2	chip_sw_kmac_app_lc	chip_sw_lc_ctrl_transition	16.045s		0	1	0.00
V2	chip_sw_kmac_app_rom	chip_sw_kmac_app_rom	36.330s	10.200us	0	1	0.00
V2	chip_sw_kmac_entropy	chip_sw_kmac_entropy	4.750m	4.518ms	1	1	100.00
V2	chip_sw_kmac_idle	chip_sw_kmac_idle	3.355m	3.960ms	1	1	100.00
V2	chip_sw_entropy_src_csrng	chip_sw_entropy_src_csrng	11.025s		0	1	0.00
V2	chip_sw_csrng_edn_cmd	chip_sw_entropy_src_csrng	11.025s		0	1	0.00
V2	chip_sw_csrng_fuse_en_sw_app_read	chip_sw_csrng_fuse_en_sw_app_read_test	12.040s		0	1	0.00
V2	chip_sw_csrng_known_answer_tests	chip_sw_csrng_kat_test	3.370m	3.993ms	1	1	100.00
V2	chip_sw_edn_entropy_reqs	chip_sw_csrng_edn_concurrency	12.037s		0	1	0.00
V2	chip_sw_keymgr_dpe_key_derivation	chip_sw_keymgr_dpe_key_derivation	5.891m	6.484ms	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	43.400s	10.200us	0	1	0.00
V2	chip_sw_otbn_op	chip_sw_otbn_ecdsa_op_irq	11.027s		0	1	0.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	11.025s		0	1	0.00
V2	chip_sw_otbn_rnd_entropy	chip_sw_otbn_randomness	4.131m	4.339ms	1	1	100.00
V2	chip_sw_otbn_urnd_entropy	chip_sw_otbn_randomness	4.131m	4.339ms	1	1	100.00
V2	chip_sw_otbn_idle	chip_sw_otbn_randomness	4.131m	4.339ms	1	1	100.00
V2	chip_sw_otbn_mem_scramble	chip_sw_otbn_mem_scramble	6.669m	5.115ms	1	1	100.00
V2	chip_sw_rom_access	chip_sw_rom_ctrl_integrity_check	7.811m	11.330ms	1	1	100.00
V2	chip_sw_rom_ctrl_integrity_check	chip_sw_rom_ctrl_integrity_check	7.811m	11.330ms	1	1	100.00
V2	chip_sw_sram_scrambled_access	chip_sw_sram_ctrl_scrambled_access	11.012s		0	1	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	11.034s		0	1	0.00
V2	chip_sw_sram_execution	chip_sw_sram_ctrl_execution_main	11.034s		0	1	0.00
V2	chip_sw_sram_lc_escalation	chip_sw_all_escalation_resets	37.130s	10.200us	0	1	0.00
		chip_sw_data_integrity_escalation	2.022m		0	1	0.00
V2	chip_otp_ctrl_init	chip_sw_lc_ctrl_transition	16.045s		0	1	0.00
V2	chip_sw_otp_ctrl_keys	chip_sw_otbn_mem_scramble	6.669m	5.115ms	1	1	100.00
		chip_sw_keymgr_dpe_key_derivation	5.891m	6.484ms	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access	11.012s		0	1	0.00
		chip_sw_rv_core_ibex_icache_invalidate	11.022s		0	1	0.00
V2	chip_sw_otp_ctrl_entropy	chip_sw_otbn_mem_scramble	6.669m	5.115ms	1	1	100.00
		chip_sw_keymgr_dpe_key_derivation	5.891m	6.484ms	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access	11.012s		0	1	0.00
		chip_sw_rv_core_ibex_icache_invalidate	11.022s		0	1	0.00
V2	chip_sw_otp_ctrl_program	chip_sw_lc_ctrl_transition	16.045s		0	1	0.00
V2	chip_sw_otp_ctrl_program_error	chip_sw_lc_ctrl_program_error	11.042s		0	1	0.00
V2	chip_sw_otp_ctrl_hw_cfg	chip_sw_lc_ctrl_otp_hw_cfg	37.173s		0	1	0.00
V2	chip_sw_otp_ctrl_lc_signals	chip_sw_otp_ctrl_lc_signals_test_unlocked0	19.092s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_dev	15.067s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_prod	13.047s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_rma	13.044s		0	1	0.00
		chip_sw_lc_ctrl_transition	16.045s		0	1	0.00
		chip_prim_tl_access	8.638m	13.660ms	1	1	100.00
V2	chip_sw_otp_prim_tl_access	chip_prim_tl_access	8.638m	13.660ms	1	1	100.00
V2	chip_sw_otp_ctrl_nvm_cnt	chip_sw_otp_ctrl_nvm_cnt	25.081s		0	1	0.00
V2	chip_sw_otp_ctrl_sw_parts	chip_sw_otp_ctrl_sw_parts	25.080s		0	1	0.00
V2	chip_sw_ast_clk_outputs	chip_sw_ast_clk_outputs	11.044s		0	1	0.00
V2	chip_sw_ast_sys_clk_jitter	chip_sw_otbn_ecdsa_op_irq_jitter_en	11.025s		0	1	0.00
		chip_sw_aes_enc_jitter_en	43.150s	10.200us	0	1	0.00
		chip_sw_hmac_enc_jitter_en	43.570s	10.200us	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	43.400s	10.200us	0	1	0.00
		chip_sw_kmac_mode_kmac_jitter_en	43.410s	10.200us	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	11.034s		0	1	0.00
		chip_sw_clkmgr_jitter	3.179m	3.929ms	1	1	100.00
V2	chip_sw_soc_proxy_external_reset_requests	chip_sw_soc_proxy_smoketest	12.042s		0	1	0.00
V2	chip_sw_soc_proxy_external_irqs	chip_sw_soc_proxy_smoketest	12.042s		0	1	0.00
V2	chip_sw_soc_proxy_external_alerts	chip_sw_soc_proxy_external_alerts	11.037s		0	1	0.00
V2	chip_sw_soc_proxy_external_wakeup_requests	chip_sw_soc_proxy_external_wakeup	12.041s		0	1	0.00
V2	chip_sw_soc_proxy_gpios	chip_sw_soc_proxy_gpios	11.038s		0	1	0.00
V2	chip_sw_nmi_irq	chip_sw_rv_core_ibex_nmi_irq	6.529m	5.098ms	0	1	0.00
V2	chip_sw_rv_core_ibex_rnd	chip_sw_rv_core_ibex_rnd	3.625m	4.134ms	1	1	100.00
V2	chip_sw_rv_core_ibex_address_translation	chip_sw_rv_core_ibex_address_translation	3.619m	4.154ms	1	1	100.00
V2	chip_sw_rv_core_ibex_icache_scrambled_access	chip_sw_rv_core_ibex_icache_invalidate	11.022s		0	1	0.00
V2	chip_sw_rv_core_ibex_fault_dump	chip_sw_rstmgr_cpu_info	20.914m	20.027ms	0	1	0.00
V2	chip_sw_rv_core_ibex_double_fault	chip_sw_rstmgr_cpu_info	20.914m	20.027ms	0	1	0.00
V2	chip_sw_smoketest	chip_sw_aes_smoketest	3.311m	4.074ms	1	1	100.00
		chip_sw_aon_timer_smoketest	3.366m	4.195ms	1	1	100.00
		chip_sw_clkmgr_smoketest	2.782m	3.944ms	1	1	100.00
		chip_sw_csrng_smoketest	2.852m	3.958ms	1	1	100.00
		chip_sw_gpio_smoketest	3.056m	4.088ms	1	1	100.00
		chip_sw_hmac_smoketest	3.400m	4.334ms	1	1	100.00
		chip_sw_kmac_smoketest	3.306m	4.213ms	1	1	100.00
		chip_sw_otbn_smoketest	4.210m	4.660ms	1	1	100.00
		chip_sw_otp_ctrl_smoketest	2.879m	3.986ms	1	1	100.00
		chip_sw_rv_plic_smoketest	3.005m	3.961ms	1	1	100.00
		chip_sw_rv_timer_smoketest	3.947m	5.035ms	1	1	100.00
		chip_sw_rstmgr_smoketest	2.654m	3.926ms	1	1	100.00
		chip_sw_sram_ctrl_smoketest	2.930m	3.964ms	1	1	100.00
		chip_sw_uart_smoketest	3.060m	4.073ms	1	1	100.00
V2	chip_sw_rom_functests	rom_keymgr_functest	13.127s		0	1	0.00
V2	chip_sw_signed	chip_sw_uart_smoketest_signed	11.126s		0	1	0.00
V2	chip_sw_boot	chip_sw_uart_tx_rx_bootstrap	45.055s		0	1	0.00
V2	chip_sw_secure_boot	base_rom_e2e_smoke	11.031s		0	1	0.00
V2	chip_lc_scrap	chip_sw_lc_ctrl_rma_to_scrap	3.113m	4.375ms	1	1	100.00
		chip_sw_lc_ctrl_raw_to_scrap	3.246m	4.656ms	1	1	100.00
		chip_sw_lc_ctrl_test_locked0_to_scrap	2.942m	4.656ms	1	1	100.00
		chip_sw_lc_ctrl_rand_to_scrap	3.282m	4.656ms	1	1	100.00
V2	chip_lc_test_locked	chip_sw_lc_walkthrough_testunlocks	12.055s		0	1	0.00
		chip_rv_dm_lc_disabled	10.035m	17.314ms	1	1	100.00
V2	chip_sw_lc_walkthrough	chip_sw_lc_walkthrough_dev	22.087s		0	1	0.00
		chip_sw_lc_walkthrough_prod	12.046s		0	1	0.00
		chip_sw_lc_walkthrough_prodend	12.046s		0	1	0.00
		chip_sw_lc_walkthrough_rma	16.082s		0	1	0.00
		chip_sw_lc_walkthrough_testunlocks	12.055s		0	1	0.00
V2	chip_sw_lc_ctrl_volatile_raw_unlock	chip_sw_lc_ctrl_volatile_raw_unlock	16.061s		0	1	0.00
		chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	13.065s		0	1	0.00
		rom_volatile_raw_unlock	10.102s		0	1	0.00
V2	chip_sw_rom_raw_unlock	rom_raw_unlock	10.113s		0	1	0.00
V2	chip_sw_exit_test_unlocked_bootstrap	chip_sw_exit_test_unlocked_bootstrap	1.137m		0	1	0.00
V2	chip_sw_inject_scramble_seed	chip_sw_inject_scramble_seed	22.039s		0	1	0.00
V2	tl_d_oob_addr_access	chip_tl_errors	2.406m	3.702ms	0	1	0.00
V2	tl_d_illegal_access	chip_tl_errors	2.406m	3.702ms	0	1	0.00
V2	tl_d_outstanding_access	chip_csr_aliasing	9.450s		0	1	0.00
		chip_same_csr_outstanding	9.380s		0	1	0.00
V2	tl_d_partial_access	chip_csr_aliasing	9.450s		0	1	0.00
		chip_same_csr_outstanding	9.380s		0	1	0.00
V2	xbar_base_random_sequence	xbar_random	2.821m	510.675us	1	1	100.00
V2	xbar_random_delay	xbar_smoke_zero_delays	8.120s	10.734us	1	1	100.00
		xbar_smoke_large_delays	3.644m	2.073ms	1	1	100.00
		xbar_smoke_slow_rsp	4.495m	1.822ms	1	1	100.00
		xbar_random_zero_delays	1.271m	74.809us	1	1	100.00
		xbar_random_large_delays	22.524m	12.543ms	1	1	100.00
		xbar_random_slow_rsp	35.683m	14.519ms	1	1	100.00
V2	xbar_unmapped_address	xbar_unmapped_addr	1.732m	221.513us	1	1	100.00
		xbar_error_and_unmapped_addr	1.483m	221.797us	1	1	100.00
V2	xbar_error_cases	xbar_error_random	2.761m	510.675us	1	1	100.00
		xbar_error_and_unmapped_addr	1.483m	221.797us	1	1	100.00
V2	xbar_all_access_same_device	xbar_access_same_device	4.767m	835.777us	1	1	100.00
		xbar_access_same_device_slow_rsp			0	1	0.00
V2	xbar_all_hosts_use_same_source_id	xbar_same_source	1.041m	199.661us	1	1	100.00
V2	xbar_stress_all	xbar_stress_all	10.303m	1.684ms	1	1	100.00
		xbar_stress_all_with_error	8.938m	1.684ms	1	1	100.00
V2	xbar_stress_with_reset	xbar_stress_all_with_rand_reset	26.647m	2.771ms	1	1	100.00
		xbar_stress_all_with_reset_error	23.046m	2.777ms	1	1	100.00
V2	rom_e2e_smoke	rom_e2e_smoke	11.042s		0	1	0.00
V2	rom_e2e_shutdown_output	rom_e2e_shutdown_output	11.042s		0	1	0.00
V2	rom_e2e_shutdown_exception_c	rom_e2e_shutdown_exception_c	11.042s		0	1	0.00
V2	rom_e2e_boot_policy_valid	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	11.054s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_dev	11.060s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod	11.066s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod_end	11.077s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_rma	11.081s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	11.082s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_dev	11.078s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod	11.073s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	10.075s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_rma	11.071s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	11.066s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_dev	11.062s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod	10.055s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	11.074s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_rma	10.062s		0	1	0.00
V2	rom_e2e_sigverify_always	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	10.061s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_dev	11.064s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod	15.075s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod_end	13.071s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_rma	11.059s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	11.055s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_dev	11.051s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod	11.068s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	12.076s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_rma	11.065s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	15.108s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_dev	11.099s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod	11.098s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	11.095s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_rma	11.093s		0	1	0.00
V2	rom_e2e_asm_init	rom_e2e_asm_init_test_unlocked0	11.091s		0	1	0.00
		rom_e2e_asm_init_dev	11.118s		0	1	0.00
		rom_e2e_asm_init_prod	11.178s		0	1	0.00
		rom_e2e_asm_init_prod_end	11.190s		0	1	0.00
		rom_e2e_asm_init_rma	11.170s		0	1	0.00
V2	rom_e2e_keymgr_init	rom_e2e_keymgr_init_rom_ext_meas	10.149s		0	1	0.00
		rom_e2e_keymgr_init_rom_ext_no_meas	10.098s		0	1	0.00
		rom_e2e_keymgr_init_rom_ext_invalid_meas	10.096s		0	1	0.00
V2	rom_e2e_static_critical	rom_e2e_static_critical	11.156s		0	1	0.00
V2		TOTAL			59	206	28.64
V2S	chip_sw_aes_masking_off	chip_sw_aes_masking_off	4.019m	4.087ms	1	1	100.00
V2S	chip_sw_rv_core_ibex_lockstep_glitch	chip_sw_rv_core_ibex_lockstep_glitch	3.203m	3.926ms	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	chip_rv_dm_perform_debug	rom_e2e_jtag_debug_test_unlocked0	10.168s		0	1	0.00
		rom_e2e_jtag_debug_dev	10.165s		0	1	0.00
		rom_e2e_jtag_debug_rma	10.153s		0	1	0.00
V3	chip_sw_rv_dm_access_after_hw_reset	chip_sw_rv_dm_access_after_escalation_reset	11.038s		0	1	0.00
V3	chip_sw_plic_alerts	chip_sw_all_escalation_resets	37.130s	10.200us	0	1	0.00
V3	chip_sw_otp_ctrl_vendor_test_csr_access	chip_sw_otp_ctrl_vendor_test_csr_access	33.119s		0	1	0.00
V3	chip_sw_otp_ctrl_escalation	chip_sw_otp_ctrl_escalation	14.344m	13.177ms	1	1	100.00
V3	chip_sw_coremark	chip_sw_coremark	10.042s		0	1	0.00
V3	chip_sw_power_max_load	chip_sw_power_virus	11.027s		0	1	0.00
V3	rom_e2e_debug	rom_e2e_jtag_debug_test_unlocked0	10.168s		0	1	0.00
		rom_e2e_jtag_debug_dev	10.165s		0	1	0.00
		rom_e2e_jtag_debug_rma	10.153s		0	1	0.00
V3	rom_e2e_jtag_inject	rom_e2e_jtag_inject_test_unlocked0	10.149s		0	1	0.00
		rom_e2e_jtag_inject_dev	10.145s		0	1	0.00
		rom_e2e_jtag_inject_rma	10.141s		0	1	0.00
V3	rom_e2e_self_hash	rom_e2e_self_hash	11.130s		0	1	0.00
V3		TOTAL			1	12	8.33
	Unmapped tests	chip_sw_rstmgr_rst_cnsty_escalation	2.105m		0	1	0.00
		chip_sw_dma_inline_hashing	3.444m	4.419ms	1	1	100.00
		chip_sw_dma_abort	3.468m	4.205ms	0	1	0.00
		rom_e2e_sigverify_mod_exp_test_unlocked0_otbn	10.093s		0	1	0.00
		rom_e2e_sigverify_mod_exp_test_unlocked0_sw	10.108s		0	1	0.00
		rom_e2e_sigverify_mod_exp_dev_otbn	10.107s		0	1	0.00
		rom_e2e_sigverify_mod_exp_dev_sw	10.106s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_otbn	10.108s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_sw	11.130s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_end_otbn	10.100s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_end_sw	10.097s		0	1	0.00
		rom_e2e_sigverify_mod_exp_rma_otbn	10.096s		0	1	0.00
		rom_e2e_sigverify_mod_exp_rma_sw	11.131s		0	1	0.00
		chip_sw_mbx_smoketest	3.562m	4.345ms	1	1	100.00
		TOTAL			66	246	26.83

Failure Buckets

Job returned non-zero exit code has 154 failures:

Test chip_sw_example_rom has 1 failures.

0.chip_sw_example_rom.1
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_example_rom/latest/run.log

  Target //sw/device/tests:example_test_from_rom_sim_dv failed to build
  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests:example_test_from_rom_sim_dv' failed; build aborted: Target //sw/device/tests:example_test_from_rom_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests:example_test_from_rom_sim_dv (cd133b)
      //hw/top_earlgrey/sw/autogen:top_earlgrey (08910b)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 59.099s, Critical Path: 0.07s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_example_manufacturer has 1 failures.

0.chip_sw_example_manufacturer.1
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_example_manufacturer/latest/run.log

  Building "@manufacturer_test_hooks//:example_test_sim_dv" on network connected machine.
  Building with command: ./bazelisk.sh build --//hw/top=darjeeling --//hw/top=darjeeling --define DISABLE_VERILATOR_BUILD=true --//util/design/data:img_seed=1 @manufacturer_test_hooks//:example_test_sim_dv
  Another command (pid=926334) is running. Waiting for it to complete on the server (server_pid=886908)...
  Another command (pid=928929) is running. Waiting for it to complete on the server (server_pid=886908)...
  Another command (pid=927663) is running. Waiting for it to complete on the server (server_pid=886908)...
  Another command (pid=927818) is running. Waiting for it to complete on the server (server_pid=886908)...

  Server terminated abruptly (error code: 14, error message: 'Socket closed', log file: '/nightly/runs/.cache/bazel/_bazel_root/4648b3ce067cc84295a1e3b10ceaf366/server/jvm.out')

  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 37

Test chip_sw_example_concurrency has 1 failures.

0.chip_sw_example_concurrency.1
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_example_concurrency/latest/run.log

      at java.base/java.util.concurrent.ForkJoinPool.deregisterWorker(Unknown Source)
      at java.base/java.util.concurrent.ForkJoinWorkerThread.run(Unknown Source)
  ERROR: /nightly/runs/opentitan/sw/device/tests/BUILD:1614:15: Compiling sw/device/tests/example_concurrency_test.c failed: (Exit -1): riscv32-unknown-elf-clang failed: error executing CppCompile command (from target //sw/device/tests:example_concurrency_test_sim_dv) external/+lowrisc_rv32imcb_toolchain+lowrisc_rv32imcb_toolchain/bin/riscv32-unknown-elf-clang -isystem external/+lowrisc_rv32imcb_toolchain+lowrisc_rv32imcb_toolchain/lib/clang/16/include -isystem ... (remaining 90 arguments skipped)

  Use --sandbox_debug to see verbose messages from the sandbox and retain the sandbox build root for debugging
  Action failed to execute: java.io.IOException: Cannot run program "/nightly/runs/.cache/bazel/_bazel_root/install/3fd603d608c2d3b856ea3d982b11227c/process-wrapper" (in directory "/nightly/runs/.cache/bazel/_bazel_root/4648b3ce067cc84295a1e3b10ceaf366/sandbox/processwrapper-sandbox/1352/execroot/_main"): error=11, Resource temporarily unavailable

  Server terminated abruptly (error code: 14, error message: 'recvmsg:Connection reset by peer', log file: '/nightly/runs/.cache/bazel/_bazel_root/4648b3ce067cc84295a1e3b10ceaf366/server/jvm.out')

  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 37

Test chip_sw_rstmgr_rst_cnsty_escalation has 1 failures.

0.chip_sw_rstmgr_rst_cnsty_escalation.1
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rstmgr_rst_cnsty_escalation/latest/run.log

  Building "//sw/device/tests/sim_dv:all_escalation_resets_test_sim_dv" on network connected machine.
  Building with command: ./bazelisk.sh build --//hw/top=darjeeling --//hw/top=darjeeling --define DISABLE_VERILATOR_BUILD=true --//util/design/data:img_seed=1 //sw/device/tests/sim_dv:all_escalation_resets_test_sim_dv
  Another command (pid=926334) is running. Waiting for it to complete on the server (server_pid=886908)...
  Another command (pid=929367) is running. Waiting for it to complete on the server (server_pid=886908)...
  Another command (pid=927663) is running. Waiting for it to complete on the server (server_pid=886908)...
  Another command (pid=927818) is running. Waiting for it to complete on the server (server_pid=886908)...

  Server terminated abruptly (error code: 14, error message: 'Socket closed', log file: '/nightly/runs/.cache/bazel/_bazel_root/4648b3ce067cc84295a1e3b10ceaf366/server/jvm.out')

  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 37

Test chip_sw_data_integrity_escalation has 1 failures.

0.chip_sw_data_integrity_escalation.1
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_data_integrity_escalation/latest/run.log

  Building "//sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv" on network connected machine.
  Building with command: ./bazelisk.sh build --//hw/top=darjeeling --//hw/top=darjeeling --define DISABLE_VERILATOR_BUILD=true --//util/design/data:img_seed=1 //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv
  Another command (pid=926334) is running. Waiting for it to complete on the server (server_pid=886908)...
  Another command (pid=929367) is running. Waiting for it to complete on the server (server_pid=886908)...
  Another command (pid=927663) is running. Waiting for it to complete on the server (server_pid=886908)...
  Another command (pid=927818) is running. Waiting for it to complete on the server (server_pid=886908)...

  Server terminated abruptly (error code: 14, error message: 'Socket closed', log file: '/nightly/runs/.cache/bazel/_bazel_root/4648b3ce067cc84295a1e3b10ceaf366/server/jvm.out')

  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 37

... and 149 more tests.

UVM_FATAL @ * us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat" has 9 failures:

Test chip_sw_aes_enc_jitter_en has 1 failures.

0.chip_sw_aes_enc_jitter_en.1
Line 416, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aes_enc_jitter_en/latest/run.log

  UVM_FATAL @  10.200001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_hmac_enc_jitter_en has 1 failures.

0.chip_sw_hmac_enc_jitter_en.1
Line 417, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_hmac_enc_jitter_en/latest/run.log

  UVM_FATAL @  10.200001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_keymgr_dpe_key_derivation_jitter_en has 1 failures.

0.chip_sw_keymgr_dpe_key_derivation_jitter_en.1
Line 415, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation_jitter_en/latest/run.log

  UVM_FATAL @  10.200001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_kmac_mode_kmac_jitter_en has 1 failures.

0.chip_sw_kmac_mode_kmac_jitter_en.1
Line 419, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_kmac_mode_kmac_jitter_en/latest/run.log

  UVM_FATAL @  10.200001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_aes_enc_jitter_en_reduced_freq has 1 failures.

0.chip_sw_aes_enc_jitter_en_reduced_freq.1
Line 417, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aes_enc_jitter_en_reduced_freq/latest/run.log

  UVM_FATAL @  10.200001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 4 more tests.

UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode has 3 failures:

Test chip_csr_bit_bash has 1 failures.

0.chip_csr_bit_bash.1
Line 131, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_csr_bit_bash/latest/run.log

  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_csr_aliasing has 1 failures.

0.chip_csr_aliasing.1
Line 131, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_csr_aliasing/latest/run.log

  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_same_csr_outstanding has 1 failures.

0.chip_same_csr_outstanding.1
Line 131, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_same_csr_outstanding/latest/run.log

  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:489) [chip_sw_keymgr_dpe_key_derivation_vseq] Check failed keymgr_pkg::KeyWidth'(get_kmac_digest(kmac_key, data_arr)) == act_digest (* [*] vs * [*]) has 2 failures:

Test chip_sw_keymgr_dpe_key_derivation has 1 failures.

0.chip_sw_keymgr_dpe_key_derivation.1
Line 471, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation/latest/run.log

  UVM_ERROR @ 6484.268888 us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:489) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_dpe_key_derivation_vseq] Check failed keymgr_pkg::KeyWidth'(get_kmac_digest(kmac_key, data_arr)) == act_digest (76782503359706702775920760936644048806596328415806192830565565835941306859755 [0xa9c15b59451fd55d13bf972e968d368c1998784bcdce1f1c4d00909b953280eb] vs 53686074962733484890164882041587138727311469164183041060936871779201593031175 [0x76b13dda9493240a178ac5ad86dbe861c200811cc5b858e6598244b875a6ba07])
  UVM_INFO @ 6484.268888 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_keymgr_dpe_key_derivation_prod has 1 failures.

0.chip_sw_keymgr_dpe_key_derivation_prod.1
Line 467, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation_prod/latest/run.log

  UVM_ERROR @ 6484.268888 us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:489) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_dpe_key_derivation_vseq] Check failed keymgr_pkg::KeyWidth'(get_kmac_digest(kmac_key, data_arr)) == act_digest (27377812706234060074674561943138340771080653846808541204159960453483536868707 [0x3c874af8d2c4d88910f9245e416b024efff1d83e1b8ec7e63890ba28211c6563] vs 21625543928212378406025785858950303043590641895548089341125069332563696936826 [0x2fcf9fc5813ebffe66288b30a7be2a7ec6c6dacaeef510df11af35410e79e77a])
  UVM_INFO @ 6484.268888 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:525) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@46368) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 2 failures:

Test chip_jtag_csr_rw has 1 failures.

0.chip_jtag_csr_rw.1
Line 6158, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_jtag_csr_rw/latest/run.log

  UVM_ERROR @ 3683.408174 us: (cip_base_scoreboard.sv:525) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@46368) { a_addr: 'h30480000  a_data: 'h1f135537  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'hd  a_opcode: 'h1  a_user: 'h248d9  d_param: 'h0  d_source: 'hd  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 1, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 3683.408174 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_jtag_mem_access has 1 failures.

0.chip_jtag_mem_access.1
Line 6158, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_jtag_mem_access/latest/run.log

  UVM_ERROR @ 3683.408174 us: (cip_base_scoreboard.sv:525) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@46368) { a_addr: 'h30480000  a_data: 'h1f135537  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'hd  a_opcode: 'h1  a_user: 'h248d9  d_param: 'h0  d_source: 'hd  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 1, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 3683.408174 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[RamCtn0]] file all_escalation_resets_test_sim_dv.*.vmem could not be opened for r mode has 1 failures:
- Test chip_sw_all_escalation_resets has 1 failures.
  - 0.chip_sw_all_escalation_resets.1
    Line 576, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_all_escalation_resets/latest/run.log
```
  UVM_FATAL @  10.200001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[RamCtn0]] file all_escalation_resets_test_sim_dv.32.vmem could not be opened for r mode
  UVM_INFO @  10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty has 1 failures:
- Test chip_sw_spi_device_pass_through_collision has 1 failures.
  - 0.chip_sw_spi_device_pass_through_collision.1
    Line 443, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_spi_device_pass_through_collision/latest/run.log
```
  UVM_ERROR @ 4172.071448 us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty
  UVM_INFO @ 4172.071448 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (sw_logger_if.sv:527) [rstmgr_alert_info_test_sim_dv(sw/device/tests/rstmgr_alert_info_test.c:859)] unexpected reset info * has 1 failures:
- Test chip_sw_rstmgr_alert_info has 1 failures.
  - 0.chip_sw_rstmgr_alert_info.1
    Line 447, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rstmgr_alert_info/latest/run.log
```
  UVM_FATAL @ 6515.775368 us: (sw_logger_if.sv:527) [rstmgr_alert_info_test_sim_dv(sw/device/tests/rstmgr_alert_info_test.c:859)] unexpected reset info 20
  UVM_INFO @ 6515.775368 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_base_vseq.sv:374) virtual_sequencer [chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns has 1 failures:
- Test chip_sw_rstmgr_cpu_info has 1 failures.
  - 0.chip_sw_rstmgr_cpu_info.1
    Line 479, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rstmgr_cpu_info/latest/run.log
```
  UVM_ERROR @ 20026.586846 us: (chip_sw_base_vseq.sv:374) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 20000000 ns

  UVM_INFO @ 20026.586846 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [rv_core_ibex_nmi_irq_test_sim_dv(sw/device/tests/rv_core_ibex_nmi_irq_test.c:172)] CHECK-fail: Timed out after * usec (* CPU cycles) waiting for nmi_fired has 1 failures:
- Test chip_sw_rv_core_ibex_nmi_irq has 1 failures.
  - 0.chip_sw_rv_core_ibex_nmi_irq.1
    Line 431, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rv_core_ibex_nmi_irq/latest/run.log
```
  UVM_ERROR @ 5098.221448 us: (sw_logger_if.sv:526) [rv_core_ibex_nmi_irq_test_sim_dv(sw/device/tests/rv_core_ibex_nmi_irq_test.c:172)] CHECK-fail: Timed out after 1000 usec (100000 CPU cycles) waiting for nmi_fired
  UVM_INFO @ 5098.221448 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[RamCtn0]] file kmac_app_rom_test_sim_dv.*.vmem could not be opened for r mode has 1 failures:
- Test chip_sw_kmac_app_rom has 1 failures.
  - 0.chip_sw_kmac_app_rom.1
    Line 439, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_kmac_app_rom/latest/run.log
```
  UVM_FATAL @  10.200001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[RamCtn0]] file kmac_app_rom_test_sim_dv.32.vmem could not be opened for r mode
  UVM_INFO @  10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

Offending '(tl_h_i[*].a_source[(IDW - *)-:STIDW] == '0)' has 1 failures:

Test chip_tl_errors has 1 failures.

0.chip_tl_errors.1
Line 266, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_tl_errors/latest/run.log

      Offending '(tl_h_i[0].a_source[(IDW - 1)-:STIDW] == '0)'
  UVM_ERROR @ 3701.965880 us: (tlul_socket_m1.sv:101) [ASSERT FAILED] idInRange
  UVM_INFO @ 3701.965880 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Error-[CNST-CIF] Constraints inconsistency failure has 1 failures:
- Test chip_padctrl_attributes has 1 failures.
  - 0.chip_padctrl_attributes.1
    Line 312, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_padctrl_attributes/latest/run.log
```
  Error-[CNST-CIF] Constraints inconsistency failure
  ../src/lowrisc_dv_dv_lib_0/dv_base_test.sv, 95
    Constraints are inconsistent and cannot be solved.
    Please check the inconsistent constraints being printed above and rewrite
    them.
```

UVM_FATAL @ * us: sequencer [sequencer] Item_done() called with no outstanding requests. Each call to item_done() must be paired with a previous call to get_next_item(). has 1 failures:

Test chip_sw_dma_abort has 1 failures.

0.chip_sw_dma_abort.1
Line 434, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_dma_abort/latest/run.log

  UVM_FATAL @ 4204.908008 us: uvm_test_top.env.m_spi_device_agents0.sequencer [uvm_test_top.env.m_spi_device_agents0.sequencer] Item_done() called with no outstanding requests. Each call to item_done() must be paired with a previous call to get_next_item().
  UVM_INFO @ 4204.908008 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Job timed out after * minutes has 1 failures:
- Test xbar_access_same_device_slow_rsp has 1 failures.
  - 0.xbar_access_same_device_slow_rsp.1
    Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.xbar_access_same_device_slow_rsp/latest/run.log
```
  Job timed out after 60 minutes
```