AES/UNMASKED Simulation Results

Wednesday April 02 2025 17:22:48 UTC

GitHub Revision: 688b340

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	4.000s	77.140us	1	1	100.00
V1	smoke	aes_smoke	5.000s	123.382us	1	1	100.00
V1	csr_hw_reset	aes_csr_hw_reset	4.000s	78.648us	1	1	100.00
V1	csr_rw	aes_csr_rw	4.000s	70.785us	1	1	100.00
V1	csr_bit_bash	aes_csr_bit_bash	6.000s	656.670us	1	1	100.00
V1	csr_aliasing	aes_csr_aliasing	5.000s	173.590us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	4.000s	240.651us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	4.000s	70.785us	1	1	100.00
		aes_csr_aliasing	5.000s	173.590us	1	1	100.00
V1		TOTAL			7	7	100.00
V2	algorithm	aes_smoke	5.000s	123.382us	1	1	100.00
		aes_config_error	5.000s	122.339us	1	1	100.00
		aes_stress	5.000s	83.876us	1	1	100.00
V2	key_length	aes_smoke	5.000s	123.382us	1	1	100.00
		aes_config_error	5.000s	122.339us	1	1	100.00
		aes_stress	5.000s	83.876us	1	1	100.00
V2	back2back	aes_stress	5.000s	83.876us	1	1	100.00
		aes_b2b	6.000s	89.821us	1	1	100.00
V2	backpressure	aes_stress	5.000s	83.876us	1	1	100.00
V2	multi_message	aes_smoke	5.000s	123.382us	1	1	100.00
		aes_config_error	5.000s	122.339us	1	1	100.00
		aes_stress	5.000s	83.876us	1	1	100.00
		aes_alert_reset	6.000s	259.409us	1	1	100.00
V2	failure_test	aes_man_cfg_err	5.000s	59.122us	1	1	100.00
		aes_config_error	5.000s	122.339us	1	1	100.00
		aes_alert_reset	6.000s	259.409us	1	1	100.00
V2	trigger_clear_test	aes_clear	5.000s	102.417us	1	1	100.00
V2	nist_test_vectors	aes_nist_vectors	7.000s	329.188us	1	1	100.00
V2	reset_recovery	aes_alert_reset	6.000s	259.409us	1	1	100.00
V2	stress	aes_stress	5.000s	83.876us	1	1	100.00
V2	sideload	aes_stress	5.000s	83.876us	1	1	100.00
		aes_sideload	5.000s	99.769us	1	1	100.00
V2	deinitialization	aes_deinit	6.000s	137.498us	1	1	100.00
V2	stress_all	aes_stress_all	18.000s	1.735ms	1	1	100.00
V2	alert_test	aes_alert_test	4.000s	89.372us	1	1	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	5.000s	241.600us	1	1	100.00
V2	tl_d_illegal_access	aes_tl_errors	5.000s	241.600us	1	1	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	4.000s	78.648us	1	1	100.00
		aes_csr_rw	4.000s	70.785us	1	1	100.00
		aes_csr_aliasing	5.000s	173.590us	1	1	100.00
		aes_same_csr_outstanding	5.000s	221.427us	1	1	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	4.000s	78.648us	1	1	100.00
		aes_csr_rw	4.000s	70.785us	1	1	100.00
		aes_csr_aliasing	5.000s	173.590us	1	1	100.00
		aes_same_csr_outstanding	5.000s	221.427us	1	1	100.00
V2		TOTAL			13	13	100.00
V2S	reseeding	aes_reseed	5.000s	183.456us	1	1	100.00
V2S	fault_inject	aes_fi	4.000s	101.946us	1	1	100.00
		aes_control_fi	4.000s	61.608us	1	1	100.00
		aes_cipher_fi	4.000s	50.372us	1	1	100.00
V2S	shadow_reg_update_error	aes_shadow_reg_errors	4.000s	3.460us	0	1	0.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	4.000s	3.460us	0	1	0.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	4.000s	3.460us	0	1	0.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	4.000s	3.460us	0	1	0.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	4.000s	21.370us	0	1	0.00
V2S	tl_intg_err	aes_sec_cm	5.000s	536.034us	1	1	100.00
		aes_tl_intg_err	4.000s	346.966us	1	1	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	4.000s	346.966us	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	6.000s	259.409us	1	1	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	4.000s	3.460us	0	1	0.00
V2S	sec_cm_main_config_sparse	aes_smoke	5.000s	123.382us	1	1	100.00
		aes_stress	5.000s	83.876us	1	1	100.00
		aes_alert_reset	6.000s	259.409us	1	1	100.00
		aes_core_fi	4.000s	69.031us	1	1	100.00
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	4.000s	3.460us	0	1	0.00
V2S	sec_cm_aux_config_regwen	aes_readability	5.000s	83.696us	1	1	100.00
		aes_stress	5.000s	83.876us	1	1	100.00
V2S	sec_cm_key_sideload	aes_stress	5.000s	83.876us	1	1	100.00
		aes_sideload	5.000s	99.769us	1	1	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	5.000s	83.696us	1	1	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	5.000s	83.696us	1	1	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	5.000s	83.696us	1	1	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	5.000s	83.696us	1	1	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	5.000s	83.696us	1	1	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	5.000s	83.876us	1	1	100.00
V2S	sec_cm_key_masking	aes_stress	5.000s	83.876us	1	1	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	4.000s	101.946us	1	1	100.00
V2S	sec_cm_main_fsm_redun	aes_fi	4.000s	101.946us	1	1	100.00
		aes_control_fi	4.000s	61.608us	1	1	100.00
		aes_cipher_fi	4.000s	50.372us	1	1	100.00
		aes_ctr_fi	4.000s	67.289us	1	1	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	4.000s	101.946us	1	1	100.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	4.000s	101.946us	1	1	100.00
		aes_control_fi	4.000s	61.608us	1	1	100.00
		aes_cipher_fi	4.000s	50.372us	1	1	100.00
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	4.000s	50.372us	1	1	100.00
V2S	sec_cm_ctr_fsm_sparse	aes_fi	4.000s	101.946us	1	1	100.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	4.000s	101.946us	1	1	100.00
		aes_control_fi	4.000s	61.608us	1	1	100.00
		aes_ctr_fi	4.000s	67.289us	1	1	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	4.000s	101.946us	1	1	100.00
		aes_control_fi	4.000s	61.608us	1	1	100.00
		aes_cipher_fi	4.000s	50.372us	1	1	100.00
		aes_ctr_fi	4.000s	67.289us	1	1	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	6.000s	259.409us	1	1	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	4.000s	101.946us	1	1	100.00
		aes_control_fi	4.000s	61.608us	1	1	100.00
		aes_cipher_fi	4.000s	50.372us	1	1	100.00
		aes_ctr_fi	4.000s	67.289us	1	1	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	4.000s	101.946us	1	1	100.00
		aes_control_fi	4.000s	61.608us	1	1	100.00
		aes_cipher_fi	4.000s	50.372us	1	1	100.00
		aes_ctr_fi	4.000s	67.289us	1	1	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	4.000s	101.946us	1	1	100.00
		aes_control_fi	4.000s	61.608us	1	1	100.00
		aes_ctr_fi	4.000s	67.289us	1	1	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	4.000s	101.946us	1	1	100.00
		aes_control_fi	4.000s	61.608us	1	1	100.00
		aes_cipher_fi	4.000s	50.372us	1	1	100.00
V2S		TOTAL			9	11	81.82
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	8.000s	331.027us	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			29	32	90.62

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:997) [aes_common_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == * (* [*] vs * [*]) fatal error fatal_fault does not trigger! has 2 failures:

  • Test aes_shadow_reg_errors has 1 failures.

    • 0.aes_shadow_reg_errors.85875587768542387603179157701407417328746190599344558309581273471173644296470
      Line 102, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/0.aes_shadow_reg_errors/latest/run.log

        UVM_ERROR @   3459797 ps: (cip_base_vseq.sv:997) [uvm_test_top.env.virtual_sequencer.aes_common_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == 1 (0 [0x0] vs 1 [0x1]) fatal error fatal_fault does not trigger!
        UVM_INFO @   3459797 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test aes_shadow_reg_errors_with_csr_rw has 1 failures.

    • 0.aes_shadow_reg_errors_with_csr_rw.58669224383835691528855170952755599413939587783073008304974288669599601942291
      Line 102, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/0.aes_shadow_reg_errors_with_csr_rw/latest/run.log

        UVM_ERROR @  21369936 ps: (cip_base_vseq.sv:997) [uvm_test_top.env.virtual_sequencer.aes_common_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == 1 (0 [0x0] vs 1 [0x1]) fatal error fatal_fault does not trigger!
        UVM_INFO @  21369936 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 1 failures:

  • Test aes_stress_all_with_rand_reset has 1 failures.

    • 0.aes_stress_all_with_rand_reset.94356942133090773812466855481113448646694709942355796647880544965175079264426
      Line 524, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 331027187 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
        UVM_INFO @ 331027187 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---