DMA Simulation Results

Wednesday April 02 2025 17:22:48 UTC

GitHub Revision: 688b340

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 dma_memory_smoke dma_memory_smoke 7.000s 1.183ms 1 1 100.00
V1 dma_handshake_smoke dma_handshake_smoke 7.000s 817.062us 1 1 100.00
V1 dma_generic_smoke dma_generic_smoke 7.000s 709.160us 1 1 100.00
V1 csr_hw_reset dma_csr_hw_reset 4.000s 52.073us 1 1 100.00
V1 csr_rw dma_csr_rw 4.000s 24.880us 1 1 100.00
V1 csr_bit_bash dma_csr_bit_bash 15.000s 1.547ms 1 1 100.00
V1 csr_aliasing dma_csr_aliasing 6.000s 319.809us 1 1 100.00
V1 csr_mem_rw_with_rand_reset dma_csr_mem_rw_with_rand_reset 4.000s 43.132us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr dma_csr_rw 4.000s 24.880us 1 1 100.00
dma_csr_aliasing 6.000s 319.809us 1 1 100.00
V1 TOTAL 8 8 100.00
V2 dma_memory_region_lock dma_memory_region_lock 48.000s 3.850ms 1 1 100.00
V2 dma_handshake_stress dma_handshake_stress 0 1 0.00
V2 dma_memory_stress dma_memory_stress 2.850m 13.227ms 1 1 100.00
V2 dma_generic_stress dma_generic_stress 3.450m 70.636ms 1 1 100.00
V2 dma_handshake_mem_buffer_overflow dma_handshake_stress 0 1 0.00
V2 dma_abort dma_abort 12.000s 2.520ms 1 1 100.00
V2 dma_stress_all dma_stress_all 2.983m 27.726ms 1 1 100.00
V2 intr_test dma_intr_test 4.000s 24.158us 1 1 100.00
V2 tl_d_oob_addr_access dma_tl_errors 6.000s 140.082us 1 1 100.00
V2 tl_d_illegal_access dma_tl_errors 6.000s 140.082us 1 1 100.00
V2 tl_d_outstanding_access dma_csr_hw_reset 4.000s 52.073us 1 1 100.00
dma_csr_rw 4.000s 24.880us 1 1 100.00
dma_csr_aliasing 6.000s 319.809us 1 1 100.00
dma_same_csr_outstanding 5.000s 204.189us 1 1 100.00
V2 tl_d_partial_access dma_csr_hw_reset 4.000s 52.073us 1 1 100.00
dma_csr_rw 4.000s 24.880us 1 1 100.00
dma_csr_aliasing 6.000s 319.809us 1 1 100.00
dma_same_csr_outstanding 5.000s 204.189us 1 1 100.00
V2 TOTAL 8 9 88.89
V2S dma_illegal_addr_range dma_mem_enabled 32.000s 280.662us 1 1 100.00
dma_generic_stress 3.450m 70.636ms 1 1 100.00
dma_handshake_stress 0 1 0.00
V2S tl_intg_err dma_tl_intg_err 5.000s 321.317us 1 1 100.00
V2S TOTAL 2 2 100.00
Unmapped tests dma_short_transfer 1.600m 20.619ms 1 1 100.00
dma_longer_transfer 9.000s 302.508us 1 1 100.00
TOTAL 20 21 95.24

Failure Buckets