EDN Simulation Results

Wednesday April 02 2025 17:22:48 UTC

GitHub Revision: 688b340

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke edn_smoke 1.910s 93.844us 1 1 100.00
V1 csr_hw_reset edn_csr_hw_reset 1.780s 35.113us 1 1 100.00
V1 csr_rw edn_csr_rw 1.700s 143.188us 1 1 100.00
V1 csr_bit_bash edn_csr_bit_bash 3.340s 228.900us 1 1 100.00
V1 csr_aliasing edn_csr_aliasing 2.160s 29.939us 1 1 100.00
V1 csr_mem_rw_with_rand_reset edn_csr_mem_rw_with_rand_reset 1.740s 21.784us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr edn_csr_rw 1.700s 143.188us 1 1 100.00
edn_csr_aliasing 2.160s 29.939us 1 1 100.00
V1 TOTAL 6 6 100.00
V2 firmware edn_genbits 2.320s 63.866us 1 1 100.00
V2 csrng_commands edn_genbits 2.320s 63.866us 1 1 100.00
V2 genbits edn_genbits 2.320s 63.866us 1 1 100.00
V2 interrupts edn_intr 1.660s 55.094us 1 1 100.00
V2 alerts edn_alert 2.110s 164.786us 1 1 100.00
V2 errs edn_err 1.970s 38.510us 1 1 100.00
V2 disable edn_disable 1.930s 18.779us 1 1 100.00
edn_disable_auto_req_mode 1.950s 79.558us 1 1 100.00
V2 stress_all edn_stress_all 3.910s 681.781us 1 1 100.00
V2 intr_test edn_intr_test 1.880s 14.050us 1 1 100.00
V2 alert_test edn_alert_test 1.900s 20.028us 1 1 100.00
V2 tl_d_oob_addr_access edn_tl_errors 2.680s 98.490us 1 1 100.00
V2 tl_d_illegal_access edn_tl_errors 2.680s 98.490us 1 1 100.00
V2 tl_d_outstanding_access edn_csr_hw_reset 1.780s 35.113us 1 1 100.00
edn_csr_rw 1.700s 143.188us 1 1 100.00
edn_csr_aliasing 2.160s 29.939us 1 1 100.00
edn_same_csr_outstanding 1.900s 26.843us 1 1 100.00
V2 tl_d_partial_access edn_csr_hw_reset 1.780s 35.113us 1 1 100.00
edn_csr_rw 1.700s 143.188us 1 1 100.00
edn_csr_aliasing 2.160s 29.939us 1 1 100.00
edn_same_csr_outstanding 1.900s 26.843us 1 1 100.00
V2 TOTAL 11 11 100.00
V2S tl_intg_err edn_sec_cm 7.760s 1.041ms 1 1 100.00
edn_tl_intg_err 3.190s 132.546us 1 1 100.00
V2S sec_cm_config_regwen edn_regwen 2.120s 36.025us 1 1 100.00
V2S sec_cm_config_mubi edn_alert 2.110s 164.786us 1 1 100.00
V2S sec_cm_main_sm_fsm_sparse edn_sec_cm 7.760s 1.041ms 1 1 100.00
V2S sec_cm_ack_sm_fsm_sparse edn_sec_cm 7.760s 1.041ms 1 1 100.00
V2S sec_cm_fifo_ctr_redun edn_sec_cm 7.760s 1.041ms 1 1 100.00
V2S sec_cm_ctr_redun edn_sec_cm 7.760s 1.041ms 1 1 100.00
V2S sec_cm_main_sm_ctr_local_esc edn_alert 2.110s 164.786us 1 1 100.00
edn_sec_cm 7.760s 1.041ms 1 1 100.00
V2S sec_cm_cs_rdata_bus_consistency edn_alert 2.110s 164.786us 1 1 100.00
V2S sec_cm_tile_link_bus_integrity edn_tl_intg_err 3.190s 132.546us 1 1 100.00
V2S TOTAL 3 3 100.00
V3 stress_all_with_rand_reset edn_stress_all_with_rand_reset 0 1 0.00
V3 TOTAL 0 1 0.00
TOTAL 20 21 95.24

Failure Buckets