HMAC Simulation Results

Wednesday April 02 2025 17:22:48 UTC

GitHub Revision: 688b340

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke hmac_smoke 5.160s 379.731us 1 1 100.00
V1 csr_hw_reset hmac_csr_hw_reset 1.740s 36.523us 1 1 100.00
V1 csr_rw hmac_csr_rw 1.830s 14.145us 1 1 100.00
V1 csr_bit_bash hmac_csr_bit_bash 8.370s 943.619us 1 1 100.00
V1 csr_aliasing hmac_csr_aliasing 7.420s 615.001us 1 1 100.00
V1 csr_mem_rw_with_rand_reset hmac_csr_mem_rw_with_rand_reset 1.810s 103.991us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr hmac_csr_rw 1.830s 14.145us 1 1 100.00
hmac_csr_aliasing 7.420s 615.001us 1 1 100.00
V1 TOTAL 6 6 100.00
V2 long_msg hmac_long_msg 3.510s 329.241us 1 1 100.00
V2 back_pressure hmac_back_pressure 25.540s 626.033us 1 1 100.00
V2 test_vectors hmac_test_sha256_vectors 8.620s 712.703us 1 1 100.00
hmac_test_sha384_vectors 6.891m 262.152ms 1 1 100.00
hmac_test_sha512_vectors 22.430s 955.875us 1 1 100.00
hmac_test_hmac256_vectors 9.580s 276.277us 1 1 100.00
hmac_test_hmac384_vectors 10.340s 326.197us 1 1 100.00
hmac_test_hmac512_vectors 18.800s 1.631ms 1 1 100.00
V2 burst_wr hmac_burst_wr 21.870s 2.267ms 1 1 100.00
V2 datapath_stress hmac_datapath_stress 2.647m 2.312ms 1 1 100.00
V2 error hmac_error 19.580s 7.298ms 1 1 100.00
V2 wipe_secret hmac_wipe_secret 19.030s 3.602ms 1 1 100.00
V2 save_and_restore hmac_smoke 5.160s 379.731us 1 1 100.00
hmac_long_msg 3.510s 329.241us 1 1 100.00
hmac_back_pressure 25.540s 626.033us 1 1 100.00
hmac_datapath_stress 2.647m 2.312ms 1 1 100.00
hmac_burst_wr 21.870s 2.267ms 1 1 100.00
hmac_stress_all 6.968m 43.654ms 1 1 100.00
V2 fifo_empty_status_interrupt hmac_smoke 5.160s 379.731us 1 1 100.00
hmac_long_msg 3.510s 329.241us 1 1 100.00
hmac_back_pressure 25.540s 626.033us 1 1 100.00
hmac_datapath_stress 2.647m 2.312ms 1 1 100.00
hmac_wipe_secret 19.030s 3.602ms 1 1 100.00
hmac_test_sha256_vectors 8.620s 712.703us 1 1 100.00
hmac_test_sha384_vectors 6.891m 262.152ms 1 1 100.00
hmac_test_sha512_vectors 22.430s 955.875us 1 1 100.00
hmac_test_hmac256_vectors 9.580s 276.277us 1 1 100.00
hmac_test_hmac384_vectors 10.340s 326.197us 1 1 100.00
hmac_test_hmac512_vectors 18.800s 1.631ms 1 1 100.00
V2 wide_digest_configurable_key_length hmac_smoke 5.160s 379.731us 1 1 100.00
hmac_long_msg 3.510s 329.241us 1 1 100.00
hmac_back_pressure 25.540s 626.033us 1 1 100.00
hmac_datapath_stress 2.647m 2.312ms 1 1 100.00
hmac_burst_wr 21.870s 2.267ms 1 1 100.00
hmac_error 19.580s 7.298ms 1 1 100.00
hmac_wipe_secret 19.030s 3.602ms 1 1 100.00
hmac_test_sha256_vectors 8.620s 712.703us 1 1 100.00
hmac_test_sha384_vectors 6.891m 262.152ms 1 1 100.00
hmac_test_sha512_vectors 22.430s 955.875us 1 1 100.00
hmac_test_hmac256_vectors 9.580s 276.277us 1 1 100.00
hmac_test_hmac384_vectors 10.340s 326.197us 1 1 100.00
hmac_test_hmac512_vectors 18.800s 1.631ms 1 1 100.00
hmac_stress_all 6.968m 43.654ms 1 1 100.00
V2 stress_all hmac_stress_all 6.968m 43.654ms 1 1 100.00
V2 alert_test hmac_alert_test 1.730s 42.841us 1 1 100.00
V2 intr_test hmac_intr_test 1.540s 13.259us 1 1 100.00
V2 tl_d_oob_addr_access hmac_tl_errors 2.890s 156.570us 1 1 100.00
V2 tl_d_illegal_access hmac_tl_errors 2.890s 156.570us 1 1 100.00
V2 tl_d_outstanding_access hmac_csr_hw_reset 1.740s 36.523us 1 1 100.00
hmac_csr_rw 1.830s 14.145us 1 1 100.00
hmac_csr_aliasing 7.420s 615.001us 1 1 100.00
hmac_same_csr_outstanding 2.500s 87.750us 1 1 100.00
V2 tl_d_partial_access hmac_csr_hw_reset 1.740s 36.523us 1 1 100.00
hmac_csr_rw 1.830s 14.145us 1 1 100.00
hmac_csr_aliasing 7.420s 615.001us 1 1 100.00
hmac_same_csr_outstanding 2.500s 87.750us 1 1 100.00
V2 TOTAL 17 17 100.00
V2S tl_intg_err hmac_sec_cm 2.020s 158.895us 1 1 100.00
hmac_tl_intg_err 4.280s 575.229us 1 1 100.00
V2S sec_cm_bus_integrity hmac_tl_intg_err 4.280s 575.229us 1 1 100.00
V2S TOTAL 2 2 100.00
V3 write_config_and_secret_key_during_msg_wr hmac_smoke 5.160s 379.731us 1 1 100.00
V3 stress_reset hmac_stress_reset 4.300s 286.943us 1 1 100.00
V3 stress_all_with_rand_reset hmac_stress_all_with_rand_reset 2.062m 2.651ms 1 1 100.00
V3 TOTAL 2 2 100.00
Unmapped tests hmac_directed 2.150s 24.818us 1 1 100.00
TOTAL 28 28 100.00