I2C Simulation Results

Wednesday April 02 2025 17:22:48 UTC

GitHub Revision: `688b340`

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	host_smoke	i2c_host_smoke	22.170s	8.299ms	1	1	100.00
V1	target_smoke	i2c_target_smoke	7.370s	1.688ms	1	1	100.00
V1	csr_hw_reset	i2c_csr_hw_reset	1.560s	22.037us	1	1	100.00
V1	csr_rw	i2c_csr_rw	1.720s	52.947us	1	1	100.00
V1	csr_bit_bash	i2c_csr_bit_bash	4.010s	960.376us	1	1	100.00
V1	csr_aliasing	i2c_csr_aliasing	2.070s	389.360us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	i2c_csr_mem_rw_with_rand_reset	2.050s	68.483us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	i2c_csr_rw	1.720s	52.947us	1	1	100.00
		i2c_csr_aliasing	2.070s	389.360us	1	1	100.00
V1		TOTAL			7	7	100.00
V2	host_error_intr	i2c_host_error_intr	2.490s	98.242us	1	1	100.00
V2	host_stress_all	i2c_host_stress_all	7.564m	28.424ms	0	1	0.00
V2	host_maxperf	i2c_host_perf	1.028m	6.818ms	1	1	100.00
V2	host_override	i2c_host_override	1.670s	48.640us	1	1	100.00
V2	host_fifo_watermark	i2c_host_fifo_watermark	1.350m	22.415ms	1	1	100.00
V2	host_fifo_overflow	i2c_host_fifo_overflow	55.900s	1.405ms	1	1	100.00
V2	host_fifo_reset	i2c_host_fifo_reset_fmt	2.010s	301.773us	1	1	100.00
		i2c_host_fifo_fmt_empty	4.210s	318.245us	1	1	100.00
		i2c_host_fifo_reset_rx	5.760s	666.457us	1	1	100.00
V2	host_fifo_full	i2c_host_fifo_full	37.830s	2.489ms	1	1	100.00
V2	host_timeout	i2c_host_stretch_timeout	11.300s	972.661us	1	1	100.00
V2	i2c_host_mode_toggle	i2c_host_mode_toggle	2.420s	393.506us	1	1	100.00
V2	target_glitch	i2c_target_glitch	6.600s	1.752ms	1	1	100.00
V2	target_stress_all	i2c_target_stress_all	1.664m	63.579ms	1	1	100.00
V2	target_maxperf	i2c_target_perf	3.670s	2.244ms	1	1	100.00
V2	target_fifo_empty	i2c_target_stress_rd	6.990s	510.433us	1	1	100.00
		i2c_target_intr_smoke	5.680s	4.462ms	1	1	100.00
V2	target_fifo_reset	i2c_target_fifo_reset_acq	1.840s	209.249us	1	1	100.00
		i2c_target_fifo_reset_tx	2.190s	221.143us	1	1	100.00
V2	target_fifo_full	i2c_target_stress_wr	2.860s	9.949ms	1	1	100.00
		i2c_target_stress_rd	6.990s	510.433us	1	1	100.00
		i2c_target_intr_stress_wr	14.670s	12.395ms	1	1	100.00
V2	target_timeout	i2c_target_timeout	5.410s	2.527ms	1	1	100.00
V2	target_clock_stretch	i2c_target_stretch	11.990s	3.616ms	1	1	100.00
V2	bad_address	i2c_target_bad_addr	4.730s	1.285ms	1	1	100.00
V2	target_mode_glitch	i2c_target_hrst	7.560s	10.304ms	0	1	0.00
V2	target_fifo_watermark	i2c_target_fifo_watermarks_acq	2.610s	504.955us	1	1	100.00
		i2c_target_fifo_watermarks_tx	2.130s	331.350us	1	1	100.00
V2	host_mode_config_perf	i2c_host_perf	1.028m	6.818ms	1	1	100.00
		i2c_host_perf_precise	7.100s	220.322us	1	1	100.00
V2	host_mode_clock_stretching	i2c_host_stretch_timeout	11.300s	972.661us	1	1	100.00
V2	target_mode_tx_stretch_ctrl	i2c_target_tx_stretch_ctrl	3.190s	144.913us	1	1	100.00
V2	target_mode_nack_generation	i2c_target_nack_acqfull	2.720s	932.466us	1	1	100.00
		i2c_target_nack_acqfull_addr	2.630s	2.089ms	1	1	100.00
		i2c_target_nack_txstretch	2.140s	310.868us	1	1	100.00
V2	host_mode_halt_on_nak	i2c_host_may_nack	12.460s	436.700us	1	1	100.00
V2	target_mode_smbus_maxlen	i2c_target_smbus_maxlen	2.390s	1.662ms	1	1	100.00
V2	alert_test	i2c_alert_test	1.630s	49.772us	1	1	100.00
V2	intr_test	i2c_intr_test	1.480s	36.215us	1	1	100.00
V2	tl_d_oob_addr_access	i2c_tl_errors	1.950s	47.736us	1	1	100.00
V2	tl_d_illegal_access	i2c_tl_errors	1.950s	47.736us	1	1	100.00
V2	tl_d_outstanding_access	i2c_csr_hw_reset	1.560s	22.037us	1	1	100.00
		i2c_csr_rw	1.720s	52.947us	1	1	100.00
		i2c_csr_aliasing	2.070s	389.360us	1	1	100.00
		i2c_same_csr_outstanding	1.800s	39.827us	1	1	100.00
V2	tl_d_partial_access	i2c_csr_hw_reset	1.560s	22.037us	1	1	100.00
		i2c_csr_rw	1.720s	52.947us	1	1	100.00
		i2c_csr_aliasing	2.070s	389.360us	1	1	100.00
		i2c_same_csr_outstanding	1.800s	39.827us	1	1	100.00
V2		TOTAL			36	38	94.74
V2S	tl_intg_err	i2c_tl_intg_err	2.240s	72.578us	1	1	100.00
		i2c_sec_cm	1.910s	251.246us	1	1	100.00
V2S	sec_cm_bus_integrity	i2c_tl_intg_err	2.240s	72.578us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	host_stress_all_with_rand_reset	i2c_host_stress_all_with_rand_reset	6.090s	365.168us	0	1	0.00
V3	target_error_intr	i2c_target_unexp_stop	2.110s	513.505us	0	1	0.00
V3	target_stress_all_with_rand_reset	i2c_target_stress_all_with_rand_reset	17.300s	12.852ms	0	1	0.00
V3		TOTAL			0	3	0.00
		TOTAL			45	50	90.00

Failure Buckets

UVM_ERROR (i2c_scoreboard.sv:717) [scoreboard] controller_mode_wr_obs_fifo item uncompared: has 1 failures:

Test i2c_host_stress_all has 1 failures.

0.i2c_host_stress_all.33580741926775216925975340231843409332494530710326896291964114592391255561093
Line 208, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all/latest/run.log

  UVM_ERROR @ 28424307565 ps: (i2c_scoreboard.sv:717) [uvm_test_top.env.scoreboard] controller_mode_wr_obs_fifo item uncompared:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------
  mon_dut_item    i2c_item            -     @7091958

UVM_ERROR (i2c_base_vseq.sv:1474) [i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (* [*] vs * [*]) has 1 failures:
- Test i2c_target_unexp_stop has 1 failures.
  - 0.i2c_target_unexp_stop.73390027565953703804177718581662891837366198962041671825902086885020251480401
    Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log
```
  UVM_ERROR @ 513505302 ps: (i2c_base_vseq.sv:1474) [uvm_test_top.env.virtual_sequencer.i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 513505302 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred! has 1 failures:
- Test i2c_target_hrst has 1 failures.
  - 0.i2c_target_hrst.5174840653874426731177179949626204326010578489249381460615856968929394890173
    Line 74, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_hrst/latest/run.log
```
  UVM_FATAL @ 10304156179 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
  UVM_INFO @ 10304156179 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:907) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
- Test i2c_host_stress_all_with_rand_reset has 1 failures.
  - 0.i2c_host_stress_all_with_rand_reset.43750376822058927385708710435269200487043894519540382907652976417734380623723
    Line 79, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 365168466 ps: (cip_base_vseq.sv:907) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 365168466 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:811) [i2c_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:
- Test i2c_target_stress_all_with_rand_reset has 1 failures.
  - 0.i2c_target_stress_all_with_rand_reset.66065218223498194632652893702835015141313069399897543337460879727383359611907
    Line 121, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 12851681476 ps: (cip_base_vseq.sv:811) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 12851681476 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```