688b340| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | keymgr_smoke | 2.810s | 111.124us | 1 | 1 | 100.00 |
| V1 | random | keymgr_random | 4.790s | 489.376us | 1 | 1 | 100.00 |
| V1 | csr_hw_reset | keymgr_csr_hw_reset | 1.880s | 13.211us | 1 | 1 | 100.00 |
| V1 | csr_rw | keymgr_csr_rw | 2.050s | 48.567us | 1 | 1 | 100.00 |
| V1 | csr_bit_bash | keymgr_csr_bit_bash | 6.560s | 271.820us | 1 | 1 | 100.00 |
| V1 | csr_aliasing | keymgr_csr_aliasing | 3.890s | 263.644us | 1 | 1 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | keymgr_csr_mem_rw_with_rand_reset | 2.040s | 33.571us | 1 | 1 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | keymgr_csr_rw | 2.050s | 48.567us | 1 | 1 | 100.00 |
| keymgr_csr_aliasing | 3.890s | 263.644us | 1 | 1 | 100.00 | ||
| V1 | TOTAL | 7 | 7 | 100.00 | |||
| V2 | cfgen_during_op | keymgr_cfg_regwen | 32.290s | 1.860ms | 1 | 1 | 100.00 |
| V2 | sideload | keymgr_sideload | 5.360s | 125.856us | 1 | 1 | 100.00 |
| keymgr_sideload_kmac | 3.460s | 43.639us | 1 | 1 | 100.00 | ||
| keymgr_sideload_aes | 2.660s | 192.109us | 1 | 1 | 100.00 | ||
| keymgr_sideload_otbn | 28.930s | 17.821ms | 1 | 1 | 100.00 | ||
| V2 | direct_to_disabled_state | keymgr_direct_to_disabled | 2.380s | 65.226us | 1 | 1 | 100.00 |
| V2 | lc_disable | keymgr_lc_disable | 14.600s | 1.514ms | 1 | 1 | 100.00 |
| V2 | kmac_error_response | keymgr_kmac_rsp_err | 3.180s | 52.987us | 1 | 1 | 100.00 |
| V2 | invalid_sw_input | keymgr_sw_invalid_input | 43.460s | 8.762ms | 1 | 1 | 100.00 |
| V2 | invalid_hw_input | keymgr_hwsw_invalid_input | 4.340s | 133.095us | 1 | 1 | 100.00 |
| V2 | sync_async_fault_cross | keymgr_sync_async_fault_cross | 5.490s | 297.206us | 0 | 1 | 0.00 |
| V2 | stress_all | keymgr_stress_all | 21.820s | 6.524ms | 1 | 1 | 100.00 |
| V2 | intr_test | keymgr_intr_test | 1.530s | 60.614us | 1 | 1 | 100.00 |
| V2 | alert_test | keymgr_alert_test | 1.850s | 220.748us | 1 | 1 | 100.00 |
| V2 | tl_d_oob_addr_access | keymgr_tl_errors | 2.850s | 381.089us | 1 | 1 | 100.00 |
| V2 | tl_d_illegal_access | keymgr_tl_errors | 2.850s | 381.089us | 1 | 1 | 100.00 |
| V2 | tl_d_outstanding_access | keymgr_csr_hw_reset | 1.880s | 13.211us | 1 | 1 | 100.00 |
| keymgr_csr_rw | 2.050s | 48.567us | 1 | 1 | 100.00 | ||
| keymgr_csr_aliasing | 3.890s | 263.644us | 1 | 1 | 100.00 | ||
| keymgr_same_csr_outstanding | 3.200s | 187.629us | 1 | 1 | 100.00 | ||
| V2 | tl_d_partial_access | keymgr_csr_hw_reset | 1.880s | 13.211us | 1 | 1 | 100.00 |
| keymgr_csr_rw | 2.050s | 48.567us | 1 | 1 | 100.00 | ||
| keymgr_csr_aliasing | 3.890s | 263.644us | 1 | 1 | 100.00 | ||
| keymgr_same_csr_outstanding | 3.200s | 187.629us | 1 | 1 | 100.00 | ||
| V2 | TOTAL | 15 | 16 | 93.75 | |||
| V2S | sec_cm_additional_check | keymgr_sec_cm | 7.760s | 304.803us | 1 | 1 | 100.00 |
| V2S | tl_intg_err | keymgr_sec_cm | 7.760s | 304.803us | 1 | 1 | 100.00 |
| keymgr_tl_intg_err | 5.470s | 826.428us | 1 | 1 | 100.00 | ||
| V2S | shadow_reg_update_error | keymgr_shadow_reg_errors | 1.700s | 6.016us | 0 | 1 | 0.00 |
| V2S | shadow_reg_read_clear_staged_value | keymgr_shadow_reg_errors | 1.700s | 6.016us | 0 | 1 | 0.00 |
| V2S | shadow_reg_storage_error | keymgr_shadow_reg_errors | 1.700s | 6.016us | 0 | 1 | 0.00 |
| V2S | shadowed_reset_glitch | keymgr_shadow_reg_errors | 1.700s | 6.016us | 0 | 1 | 0.00 |
| V2S | shadow_reg_update_error_with_csr_rw | keymgr_shadow_reg_errors_with_csr_rw | 2.780s | 246.217us | 0 | 1 | 0.00 |
| V2S | prim_count_check | keymgr_sec_cm | 7.760s | 304.803us | 1 | 1 | 100.00 |
| V2S | prim_fsm_check | keymgr_sec_cm | 7.760s | 304.803us | 1 | 1 | 100.00 |
| V2S | sec_cm_bus_integrity | keymgr_tl_intg_err | 5.470s | 826.428us | 1 | 1 | 100.00 |
| V2S | sec_cm_config_shadow | keymgr_shadow_reg_errors | 1.700s | 6.016us | 0 | 1 | 0.00 |
| V2S | sec_cm_op_config_regwen | keymgr_cfg_regwen | 32.290s | 1.860ms | 1 | 1 | 100.00 |
| V2S | sec_cm_reseed_config_regwen | keymgr_random | 4.790s | 489.376us | 1 | 1 | 100.00 |
| keymgr_csr_rw | 2.050s | 48.567us | 1 | 1 | 100.00 | ||
| V2S | sec_cm_sw_binding_config_regwen | keymgr_random | 4.790s | 489.376us | 1 | 1 | 100.00 |
| keymgr_csr_rw | 2.050s | 48.567us | 1 | 1 | 100.00 | ||
| V2S | sec_cm_max_key_ver_config_regwen | keymgr_random | 4.790s | 489.376us | 1 | 1 | 100.00 |
| keymgr_csr_rw | 2.050s | 48.567us | 1 | 1 | 100.00 | ||
| V2S | sec_cm_lc_ctrl_intersig_mubi | keymgr_lc_disable | 14.600s | 1.514ms | 1 | 1 | 100.00 |
| V2S | sec_cm_constants_consistency | keymgr_hwsw_invalid_input | 4.340s | 133.095us | 1 | 1 | 100.00 |
| V2S | sec_cm_intersig_consistency | keymgr_hwsw_invalid_input | 4.340s | 133.095us | 1 | 1 | 100.00 |
| V2S | sec_cm_hw_key_sw_noaccess | keymgr_random | 4.790s | 489.376us | 1 | 1 | 100.00 |
| V2S | sec_cm_output_keys_ctrl_redun | keymgr_sideload_protect | 6.930s | 753.429us | 1 | 1 | 100.00 |
| V2S | sec_cm_ctrl_fsm_sparse | keymgr_sec_cm | 7.760s | 304.803us | 1 | 1 | 100.00 |
| V2S | sec_cm_data_fsm_sparse | keymgr_sec_cm | 7.760s | 304.803us | 1 | 1 | 100.00 |
| V2S | sec_cm_ctrl_fsm_local_esc | keymgr_sec_cm | 7.760s | 304.803us | 1 | 1 | 100.00 |
| V2S | sec_cm_ctrl_fsm_consistency | keymgr_custom_cm | 3.180s | 41.535us | 0 | 1 | 0.00 |
| V2S | sec_cm_ctrl_fsm_global_esc | keymgr_lc_disable | 14.600s | 1.514ms | 1 | 1 | 100.00 |
| V2S | sec_cm_ctrl_ctr_redun | keymgr_sec_cm | 7.760s | 304.803us | 1 | 1 | 100.00 |
| V2S | sec_cm_kmac_if_fsm_sparse | keymgr_sec_cm | 7.760s | 304.803us | 1 | 1 | 100.00 |
| V2S | sec_cm_kmac_if_ctr_redun | keymgr_sec_cm | 7.760s | 304.803us | 1 | 1 | 100.00 |
| V2S | sec_cm_kmac_if_cmd_ctrl_consistency | keymgr_custom_cm | 3.180s | 41.535us | 0 | 1 | 0.00 |
| V2S | sec_cm_kmac_if_done_ctrl_consistency | keymgr_custom_cm | 3.180s | 41.535us | 0 | 1 | 0.00 |
| V2S | sec_cm_reseed_ctr_redun | keymgr_sec_cm | 7.760s | 304.803us | 1 | 1 | 100.00 |
| V2S | sec_cm_side_load_sel_ctrl_consistency | keymgr_custom_cm | 3.180s | 41.535us | 0 | 1 | 0.00 |
| V2S | sec_cm_sideload_ctrl_fsm_sparse | keymgr_sec_cm | 7.760s | 304.803us | 1 | 1 | 100.00 |
| V2S | sec_cm_ctrl_key_integrity | keymgr_custom_cm | 3.180s | 41.535us | 0 | 1 | 0.00 |
| V2S | TOTAL | 3 | 6 | 50.00 | |||
| V3 | stress_all_with_rand_reset | keymgr_stress_all_with_rand_reset | 11.780s | 967.478us | 1 | 1 | 100.00 |
| V3 | TOTAL | 1 | 1 | 100.00 | |||
| TOTAL | 26 | 30 | 86.67 |
UVM_ERROR (cip_base_vseq.sv:986) [keymgr_common_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == * (* [*] vs * [*]) fatal error fatal_fault_err does not trigger! has 2 failures:
Test keymgr_shadow_reg_errors has 1 failures.
0.keymgr_shadow_reg_errors.86318015539171946492038441303573499489193464506737818975082231909429815079499
Line 75, in log /nightly/runs/scratch/master/keymgr-sim-vcs/0.keymgr_shadow_reg_errors/latest/run.log
UVM_ERROR @ 6016180 ps: (cip_base_vseq.sv:986) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == 1 (0 [0x0] vs 1 [0x1]) fatal error fatal_fault_err does not trigger!
UVM_INFO @ 6016180 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test keymgr_shadow_reg_errors_with_csr_rw has 1 failures.
0.keymgr_shadow_reg_errors_with_csr_rw.100451133926379289578647256066925292919907625714893581187459576650417502256367
Line 77, in log /nightly/runs/scratch/master/keymgr-sim-vcs/0.keymgr_shadow_reg_errors_with_csr_rw/latest/run.log
UVM_ERROR @ 246217121 ps: (cip_base_vseq.sv:986) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == 1 (0 [0x0] vs 1 [0x1]) fatal error fatal_fault_err does not trigger!
UVM_INFO @ 246217121 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:986) [keymgr_custom_cm_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == * (* [*] vs * [*]) fatal error fatal_fault_err does not trigger! has 1 failures:
0.keymgr_custom_cm.35232067643343706038150413838386698393460329887605117087657869194104281000866
Line 243, in log /nightly/runs/scratch/master/keymgr-sim-vcs/0.keymgr_custom_cm/latest/run.log
UVM_ERROR @ 41535169 ps: (cip_base_vseq.sv:986) [uvm_test_top.env.virtual_sequencer.keymgr_custom_cm_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == 1 (0 [0x0] vs 1 [0x1]) fatal error fatal_fault_err does not trigger!
UVM_INFO @ 41535169 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:986) [keymgr_sync_async_fault_cross_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == * (* [*] vs * [*]) fatal error fatal_fault_err does not trigger! has 1 failures:
0.keymgr_sync_async_fault_cross.84795971777654691432871187332629634348778616624331058421037959344539188207929
Line 168, in log /nightly/runs/scratch/master/keymgr-sim-vcs/0.keymgr_sync_async_fault_cross/latest/run.log
UVM_ERROR @ 297206190 ps: (cip_base_vseq.sv:986) [uvm_test_top.env.virtual_sequencer.keymgr_sync_async_fault_cross_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == 1 (0 [0x0] vs 1 [0x1]) fatal error fatal_fault_err does not trigger!
UVM_INFO @ 297206190 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---