KMAC/MASKED Simulation Results

Wednesday April 02 2025 17:22:48 UTC

GitHub Revision: 688b340

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	35.470s	1.265ms	1	1	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.880s	63.308us	1	1	100.00
V1	csr_rw	kmac_csr_rw	1.950s	33.738us	1	1	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	8.300s	149.331us	1	1	100.00
V1	csr_aliasing	kmac_csr_aliasing	4.470s	934.133us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.590s	196.531us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.950s	33.738us	1	1	100.00
		kmac_csr_aliasing	4.470s	934.133us	1	1	100.00
V1	mem_walk	kmac_mem_walk	1.480s	22.583us	1	1	100.00
V1	mem_partial_access	kmac_mem_partial_access	2.270s	30.573us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	15.217m	220.561ms	1	1	100.00
V2	burst_write	kmac_burst_write	9.564m	21.550ms	1	1	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	31.903m	409.960ms	1	1	100.00
		kmac_test_vectors_sha3_256	30.820s	2.418ms	1	1	100.00
		kmac_test_vectors_sha3_384	18.930s	855.356us	1	1	100.00
		kmac_test_vectors_sha3_512	13.970m	37.822ms	1	1	100.00
		kmac_test_vectors_shake_128	2.047m	3.702ms	1	1	100.00
		kmac_test_vectors_shake_256	1.841m	7.617ms	1	1	100.00
		kmac_test_vectors_kmac	2.810s	61.440us	1	1	100.00
		kmac_test_vectors_kmac_xof	3.390s	118.046us	1	1	100.00
V2	sideload	kmac_sideload	4.837m	5.328ms	1	1	100.00
V2	app	kmac_app	1.603m	11.669ms	1	1	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	1.307m	4.618ms	1	1	100.00
V2	entropy_refresh	kmac_entropy_refresh	2.237m	12.465ms	1	1	100.00
V2	error	kmac_error	4.765m	14.879ms	1	1	100.00
V2	key_error	kmac_key_error	4.370s	905.886us	1	1	100.00
V2	sideload_invalid	kmac_sideload_invalid	2.630s	134.576us	1	1	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	25.810s	490.815us	1	1	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	2.050s	70.143us	1	1	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	44.510s	20.353ms	1	1	100.00
V2	lc_escalation	kmac_lc_escalation	1.830s	11.357us	0	1	0.00
V2	stress_all	kmac_stress_all	8.133m	8.256ms	1	1	100.00
V2	intr_test	kmac_intr_test	1.910s	11.006us	1	1	100.00
V2	alert_test	kmac_alert_test	1.900s	15.647us	1	1	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	2.700s	907.709us	1	1	100.00
V2	tl_d_illegal_access	kmac_tl_errors	2.700s	907.709us	1	1	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.880s	63.308us	1	1	100.00
		kmac_csr_rw	1.950s	33.738us	1	1	100.00
		kmac_csr_aliasing	4.470s	934.133us	1	1	100.00
		kmac_same_csr_outstanding	2.130s	26.718us	1	1	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.880s	63.308us	1	1	100.00
		kmac_csr_rw	1.950s	33.738us	1	1	100.00
		kmac_csr_aliasing	4.470s	934.133us	1	1	100.00
		kmac_same_csr_outstanding	2.130s	26.718us	1	1	100.00
V2		TOTAL			25	26	96.15
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.790s	4.888us	0	1	0.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.790s	4.888us	0	1	0.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.790s	4.888us	0	1	0.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.790s	4.888us	0	1	0.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	2.310s	25.621us	0	1	0.00
V2S	tl_intg_err	kmac_sec_cm	53.850s	9.064ms	1	1	100.00
		kmac_tl_intg_err	2.100s	81.438us	0	1	0.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	2.100s	81.438us	0	1	0.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	1.830s	11.357us	0	1	0.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	35.470s	1.265ms	1	1	100.00
V2S	sec_cm_key_sideload	kmac_sideload	4.837m	5.328ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.790s	4.888us	0	1	0.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	53.850s	9.064ms	1	1	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	53.850s	9.064ms	1	1	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	53.850s	9.064ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	35.470s	1.265ms	1	1	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	1.830s	11.357us	0	1	0.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	53.850s	9.064ms	1	1	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	1.834m	2.517ms	1	1	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	35.470s	1.265ms	1	1	100.00
V2S		TOTAL			2	5	40.00
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	39.340s	8.013ms	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			35	40	87.50

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:986) [kmac_common_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == * (* [*] vs * [*]) fatal error fatal_fault_err does not trigger! has 2 failures:

  • Test kmac_shadow_reg_errors has 1 failures.

    • 0.kmac_shadow_reg_errors.70048493481917497770995456974292931825655025788999727171411163853666523134304
      Line 75, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/0.kmac_shadow_reg_errors/latest/run.log

        UVM_ERROR @   4887876 ps: (cip_base_vseq.sv:986) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == 1 (0 [0x0] vs 1 [0x1]) fatal error fatal_fault_err does not trigger!
        UVM_INFO @   4887876 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test kmac_shadow_reg_errors_with_csr_rw has 1 failures.

    • 0.kmac_shadow_reg_errors_with_csr_rw.37678621718436154161004707485392250823581055897689104221650182244330467571871
      Line 75, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/0.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

        UVM_ERROR @  25621433 ps: (cip_base_vseq.sv:986) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == 1 (0 [0x0] vs 1 [0x1]) fatal error fatal_fault_err does not trigger!
        UVM_INFO @  25621433 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:986) [kmac_lc_escalation_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == * (* [*] vs * [*]) fatal error fatal_fault_err does not trigger! has 1 failures:

  • Test kmac_lc_escalation has 1 failures.

    • 0.kmac_lc_escalation.43155041345679974221245543540298678355102880526900272021505719855359859623429
      Line 75, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/0.kmac_lc_escalation/latest/run.log

        UVM_ERROR @  11356605 ps: (cip_base_vseq.sv:986) [uvm_test_top.env.virtual_sequencer.kmac_lc_escalation_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == 1 (0 [0x0] vs 1 [0x1]) fatal error fatal_fault_err does not trigger!
        UVM_INFO @  11356605 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (kmac_scoreboard.sv:1202) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 1 failures:

  • Test kmac_stress_all_with_rand_reset has 1 failures.

    • 0.kmac_stress_all_with_rand_reset.106184242994219717357621018785870491088257564236824714589891344647703682072017
      Line 165, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 8013008222 ps: (kmac_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483648 [0x80000000]) reg name: kmac_reg_block.err_code
        UVM_INFO @ 8013008222 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Offending '(d2h.d_error || ((d2h.d_data & *) == (exp_vals[*] & *)))' has 1 failures:

  • Test kmac_tl_intg_err has 1 failures.

    • 0.kmac_tl_intg_err.113020795922092680088788487709055833918597812056367934629889604599476208895820
      Line 90, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/0.kmac_tl_intg_err/latest/run.log

            Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[47] & 'hffffffff)))'
        UVM_ERROR @  81437549 ps: (kmac_csr_assert_fpv.sv:532) [ASSERT FAILED] prefix_8_rd_A
        UVM_INFO @  81437549 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---