KMAC/UNMASKED Simulation Results

Wednesday April 02 2025 17:22:48 UTC

GitHub Revision: 688b340

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke kmac_smoke 16.920s 1.917ms 1 1 100.00
V1 csr_hw_reset kmac_csr_hw_reset 1.750s 58.554us 1 1 100.00
V1 csr_rw kmac_csr_rw 1.760s 30.266us 1 1 100.00
V1 csr_bit_bash kmac_csr_bit_bash 13.320s 1.247ms 1 1 100.00
V1 csr_aliasing kmac_csr_aliasing 6.140s 275.785us 1 1 100.00
V1 csr_mem_rw_with_rand_reset kmac_csr_mem_rw_with_rand_reset 2.520s 248.524us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr kmac_csr_rw 1.760s 30.266us 1 1 100.00
kmac_csr_aliasing 6.140s 275.785us 1 1 100.00
V1 mem_walk kmac_mem_walk 1.670s 46.374us 1 1 100.00
V1 mem_partial_access kmac_mem_partial_access 2.100s 188.682us 1 1 100.00
V1 TOTAL 8 8 100.00
V2 long_msg_and_output kmac_long_msg_and_output 5.975m 44.713ms 1 1 100.00
V2 burst_write kmac_burst_write 2.922m 2.954ms 1 1 100.00
V2 test_vectors kmac_test_vectors_sha3_224 23.320m 116.397ms 1 1 100.00
kmac_test_vectors_sha3_256 26.370s 1.672ms 1 1 100.00
kmac_test_vectors_sha3_384 18.188m 652.788ms 1 1 100.00
kmac_test_vectors_sha3_512 12.110s 2.974ms 1 1 100.00
kmac_test_vectors_shake_128 2.258m 40.924ms 1 1 100.00
kmac_test_vectors_shake_256 4.083m 22.870ms 1 1 100.00
kmac_test_vectors_kmac 2.680s 73.533us 1 1 100.00
kmac_test_vectors_kmac_xof 2.420s 77.207us 1 1 100.00
V2 sideload kmac_sideload 1.358m 1.663ms 1 1 100.00
V2 app kmac_app 30.700s 5.289ms 1 1 100.00
V2 app_with_partial_data kmac_app_with_partial_data 13.420s 1.537ms 1 1 100.00
V2 entropy_refresh kmac_entropy_refresh 2.898m 27.060ms 1 1 100.00
V2 error kmac_error 3.069m 68.271ms 1 1 100.00
V2 key_error kmac_key_error 2.620s 675.610us 1 1 100.00
V2 sideload_invalid kmac_sideload_invalid 4.240s 845.754us 1 1 100.00
V2 edn_timeout_error kmac_edn_timeout_error 14.950s 1.480ms 1 1 100.00
V2 entropy_mode_error kmac_entropy_mode_error 24.170s 1.468ms 1 1 100.00
V2 entropy_ready_error kmac_entropy_ready_error 1.830s 77.591us 1 1 100.00
V2 lc_escalation kmac_lc_escalation 1.770s 7.373us 0 1 0.00
V2 stress_all kmac_stress_all 3.292m 14.405ms 1 1 100.00
V2 intr_test kmac_intr_test 1.520s 14.964us 1 1 100.00
V2 alert_test kmac_alert_test 1.680s 30.158us 1 1 100.00
V2 tl_d_oob_addr_access kmac_tl_errors 2.320s 124.732us 1 1 100.00
V2 tl_d_illegal_access kmac_tl_errors 2.320s 124.732us 1 1 100.00
V2 tl_d_outstanding_access kmac_csr_hw_reset 1.750s 58.554us 1 1 100.00
kmac_csr_rw 1.760s 30.266us 1 1 100.00
kmac_csr_aliasing 6.140s 275.785us 1 1 100.00
kmac_same_csr_outstanding 2.500s 440.389us 1 1 100.00
V2 tl_d_partial_access kmac_csr_hw_reset 1.750s 58.554us 1 1 100.00
kmac_csr_rw 1.760s 30.266us 1 1 100.00
kmac_csr_aliasing 6.140s 275.785us 1 1 100.00
kmac_same_csr_outstanding 2.500s 440.389us 1 1 100.00
V2 TOTAL 25 26 96.15
V2S shadow_reg_update_error kmac_shadow_reg_errors 1.580s 3.030us 0 1 0.00
V2S shadow_reg_read_clear_staged_value kmac_shadow_reg_errors 1.580s 3.030us 0 1 0.00
V2S shadow_reg_storage_error kmac_shadow_reg_errors 1.580s 3.030us 0 1 0.00
V2S shadowed_reset_glitch kmac_shadow_reg_errors 1.580s 3.030us 0 1 0.00
V2S shadow_reg_update_error_with_csr_rw kmac_shadow_reg_errors_with_csr_rw 1.510s 2.041us 0 1 0.00
V2S tl_intg_err kmac_sec_cm 19.170s 12.939ms 1 1 100.00
kmac_tl_intg_err 3.830s 617.070us 1 1 100.00
V2S sec_cm_bus_integrity kmac_tl_intg_err 3.830s 617.070us 1 1 100.00
V2S sec_cm_lc_escalate_en_intersig_mubi kmac_lc_escalation 1.770s 7.373us 0 1 0.00
V2S sec_cm_sw_key_key_masking kmac_smoke 16.920s 1.917ms 1 1 100.00
V2S sec_cm_key_sideload kmac_sideload 1.358m 1.663ms 1 1 100.00
V2S sec_cm_cfg_shadowed_config_shadow kmac_shadow_reg_errors 1.580s 3.030us 0 1 0.00
V2S sec_cm_fsm_sparse kmac_sec_cm 19.170s 12.939ms 1 1 100.00
V2S sec_cm_ctr_redun kmac_sec_cm 19.170s 12.939ms 1 1 100.00
V2S sec_cm_packer_ctr_redun kmac_sec_cm 19.170s 12.939ms 1 1 100.00
V2S sec_cm_cfg_shadowed_config_regwen kmac_smoke 16.920s 1.917ms 1 1 100.00
V2S sec_cm_fsm_global_esc kmac_lc_escalation 1.770s 7.373us 0 1 0.00
V2S sec_cm_fsm_local_esc kmac_sec_cm 19.170s 12.939ms 1 1 100.00
V2S sec_cm_absorbed_ctrl_mubi kmac_mubi 1.414m 5.192ms 1 1 100.00
V2S sec_cm_sw_cmd_ctrl_sparse kmac_smoke 16.920s 1.917ms 1 1 100.00
V2S TOTAL 3 5 60.00
V3 stress_all_with_rand_reset kmac_stress_all_with_rand_reset 2.993m 14.279ms 1 1 100.00
V3 TOTAL 1 1 100.00
TOTAL 37 40 92.50

Failure Buckets