688b340| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | mbx_smoke | mbx_smoke | 33.000s | 2.908ms | 1 | 1 | 100.00 |
| V1 | csr_hw_reset | mbx_csr_hw_reset | 4.000s | 29.382us | 1 | 1 | 100.00 |
| V1 | csr_rw | mbx_csr_rw | 3.000s | 98.903us | 1 | 1 | 100.00 |
| V1 | csr_bit_bash | mbx_csr_bit_bash | 4.000s | 84.819us | 1 | 1 | 100.00 |
| V1 | csr_aliasing | mbx_csr_aliasing | 4.000s | 46.099us | 1 | 1 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | mbx_csr_mem_rw_with_rand_reset | 3.000s | 4.177us | 0 | 1 | 0.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | mbx_csr_rw | 3.000s | 98.903us | 1 | 1 | 100.00 |
| mbx_csr_aliasing | 4.000s | 46.099us | 1 | 1 | 100.00 | ||
| V1 | TOTAL | 5 | 6 | 83.33 | |||
| V2 | mbx_stress | mbx_stress | 43.000s | 1.114ms | 1 | 1 | 100.00 |
| mbx_stress_zero_delays | 46.000s | 2.037ms | 1 | 1 | 100.00 | ||
| V2 | mbx_imbx_oob | mbx_imbx_oob | 16.000s | 1.459ms | 1 | 1 | 100.00 |
| V2 | alert_test | mbx_alert_test | 4.000s | 16.998us | 1 | 1 | 100.00 |
| V2 | tl_d_oob_addr_access | mbx_tl_errors | 3.000s | 1.050us | 0 | 1 | 0.00 |
| V2 | tl_d_illegal_access | mbx_tl_errors | 3.000s | 1.050us | 0 | 1 | 0.00 |
| V2 | tl_d_outstanding_access | mbx_csr_hw_reset | 4.000s | 29.382us | 1 | 1 | 100.00 |
| mbx_csr_rw | 3.000s | 98.903us | 1 | 1 | 100.00 | ||
| mbx_csr_aliasing | 4.000s | 46.099us | 1 | 1 | 100.00 | ||
| mbx_same_csr_outstanding | 3.000s | 43.107us | 1 | 1 | 100.00 | ||
| V2 | tl_d_partial_access | mbx_csr_hw_reset | 4.000s | 29.382us | 1 | 1 | 100.00 |
| mbx_csr_rw | 3.000s | 98.903us | 1 | 1 | 100.00 | ||
| mbx_csr_aliasing | 4.000s | 46.099us | 1 | 1 | 100.00 | ||
| mbx_same_csr_outstanding | 3.000s | 43.107us | 1 | 1 | 100.00 | ||
| V2 | TOTAL | 5 | 6 | 83.33 | |||
| V2S | tl_intg_err | mbx_sec_cm | 3.000s | 16.330us | 1 | 1 | 100.00 |
| mbx_tl_intg_err | 3.000s | 7.966us | 0 | 1 | 0.00 | ||
| V2S | TOTAL | 1 | 2 | 50.00 | |||
| TOTAL | 11 | 14 | 78.57 |
UVM_ERROR (tl_host_seq.sv:55) sequencer [tl_seq] fail to find matching req for rsp[*]: a_addr = * a_data = * a_mask = * a_size = * a_param = * a_source = * a_opcode = PutPartialData a_user = * d_data = * d_size = * d_param = * d_source = * d_opcode = AccessAckData d_error = * d_user = * d_sink = * req_abort_after_a_valid_len = * rsp_abort_after_d_valid_len = * req_completed = * rsp_completed = * has 2 failures:
Test mbx_tl_errors has 1 failures.
0.mbx_tl_errors.27219439797339978499165193267916699094782249393751741820572777735720384830074
Line 82, in log /nightly/runs/scratch/master/mbx-sim-xcelium/0.mbx_tl_errors/latest/run.log
UVM_ERROR @ 1049744 ps: (tl_host_seq.sv:55) uvm_test_top.env.m_tl_agent_mbx_mem_reg_block.sequencer [uvm_test_top.env.virtual_sequencer._item.tl_seq] fail to find matching req for rsp[0]: a_addr = 0xca55f578 a_data = 0xf175f25a a_mask = 0xf a_size = 0x2 a_param = 0x0 a_source = 0xb0 a_opcode = PutPartialData a_user = 0xc1c7 d_data = 0x39ea5838 d_size = 0x0 d_param = 0x0 d_source = 0x1a d_opcode = AccessAckData d_error = 0 d_user = 11010110010110 d_sink = 1 req_abort_after_a_valid_len = 0 rsp_abort_after_d_valid_len = 0 req_completed = 0 rsp_completed = 1
UVM_INFO @ 1049744 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test mbx_tl_intg_err has 1 failures.
0.mbx_tl_intg_err.97680138252599132929812682791893859483319349283146984306790032630387749124806
Line 95, in log /nightly/runs/scratch/master/mbx-sim-xcelium/0.mbx_tl_intg_err/latest/run.log
UVM_ERROR @ 7966313 ps: (tl_host_seq.sv:55) uvm_test_top.env.m_tl_agent_mbx_mem_reg_block.sequencer [uvm_test_top.env.virtual_sequencer._item.tl_seq] fail to find matching req for rsp[0]: a_addr = 0xd1ac9756 a_data = 0x9d8df652 a_mask = 0x8 a_size = 0x1 a_param = 0x0 a_source = 0xaa a_opcode = PutPartialData a_user = 0x7fce d_data = 0x701efd3e d_size = 0x2 d_param = 0x0 d_source = 0xbb d_opcode = AccessAckData d_error = 0 d_user = 101000111001 d_sink = 1 req_abort_after_a_valid_len = 0 rsp_abort_after_d_valid_len = 0 req_completed = 0 rsp_completed = 1
UVM_INFO @ 7966313 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (tl_host_seq.sv:55) sequencer [tl_seq] fail to find matching req for rsp[*]: a_addr = * a_data = * a_mask = * a_size = * a_param = * a_source = * a_opcode = Invalid, value: * a_user = * d_data = * d_size = * d_param = * d_source = * d_opcode = AccessAck d_error = * d_user = * d_sink = * req_abort_after_a_valid_len = * rsp_abort_after_d_valid_len = * req_completed = * rsp_completed = * has 1 failures:
0.mbx_csr_mem_rw_with_rand_reset.56312041507011796863353907286003557785930725334498775386690741495987990331351
Line 83, in log /nightly/runs/scratch/master/mbx-sim-xcelium/0.mbx_csr_mem_rw_with_rand_reset/latest/run.log
UVM_ERROR @ 4177459 ps: (tl_host_seq.sv:55) uvm_test_top.env.m_tl_agent_mbx_mem_reg_block.sequencer [uvm_test_top.env.virtual_sequencer._item.tl_seq] fail to find matching req for rsp[0]: a_addr = 0x4f288b3f a_data = 0x7e365db a_mask = 0x0 a_size = 0x0 a_param = 0x0 a_source = 0xa6 a_opcode = Invalid, value: 7 a_user = 0x24b3d d_data = 0x78621ec4 d_size = 0x0 d_param = 0x0 d_source = 0x2 d_opcode = AccessAck d_error = 0 d_user = 1100010110110 d_sink = 0 req_abort_after_a_valid_len = 1 rsp_abort_after_d_valid_len = 0 req_completed = 0 rsp_completed = 1
UVM_INFO @ 4177459 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---