OTBN Simulation Results

Wednesday April 02 2025 17:22:48 UTC

GitHub Revision: 688b340

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	otbn_smoke	12.000s	39.691us	1	1	100.00
V1	single_binary	otbn_single	15.000s	77.700us	1	1	100.00
V1	csr_hw_reset	otbn_csr_hw_reset	8.000s	16.312us	1	1	100.00
V1	csr_rw	otbn_csr_rw	6.000s	11.044us	1	1	100.00
V1	csr_bit_bash	otbn_csr_bit_bash	8.000s	277.203us	1	1	100.00
V1	csr_aliasing	otbn_csr_aliasing	6.000s	12.475us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	otbn_csr_mem_rw_with_rand_reset	10.000s	79.690us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	otbn_csr_rw	6.000s	11.044us	1	1	100.00
		otbn_csr_aliasing	6.000s	12.475us	1	1	100.00
V1	mem_walk	otbn_mem_walk	13.000s	187.281us	1	1	100.00
V1	mem_partial_access	otbn_mem_partial_access	11.000s	70.345us	1	1	100.00
V1		TOTAL			9	9	100.00
V2	reset_recovery	otbn_reset	20.000s	59.713us	1	1	100.00
V2	multi_error	otbn_multi_err	44.000s	304.703us	1	1	100.00
V2	back_to_back	otbn_multi	1.117m	386.229us	1	1	100.00
V2	stress_all	otbn_stress_all	14.000s	32.401us	1	1	100.00
V2	lc_escalation	otbn_escalate	8.000s	21.548us	1	1	100.00
V2	zero_state_err_urnd	otbn_zero_state_err_urnd	10.000s	32.912us	1	1	100.00
V2	sw_errs_fatal_chk	otbn_sw_errs_fatal_chk	10.000s	20.748us	1	1	100.00
V2	alert_test	otbn_alert_test	8.000s	15.553us	1	1	100.00
V2	intr_test	otbn_intr_test	7.000s	27.345us	1	1	100.00
V2	tl_d_oob_addr_access	otbn_tl_errors	6.000s	74.977us	1	1	100.00
V2	tl_d_illegal_access	otbn_tl_errors	6.000s	74.977us	1	1	100.00
V2	tl_d_outstanding_access	otbn_csr_hw_reset	8.000s	16.312us	1	1	100.00
		otbn_csr_rw	6.000s	11.044us	1	1	100.00
		otbn_csr_aliasing	6.000s	12.475us	1	1	100.00
		otbn_same_csr_outstanding	8.000s	25.941us	1	1	100.00
V2	tl_d_partial_access	otbn_csr_hw_reset	8.000s	16.312us	1	1	100.00
		otbn_csr_rw	6.000s	11.044us	1	1	100.00
		otbn_csr_aliasing	6.000s	12.475us	1	1	100.00
		otbn_same_csr_outstanding	8.000s	25.941us	1	1	100.00
V2		TOTAL			11	11	100.00
V2S	mem_integrity	otbn_imem_err	9.000s	69.154us	1	1	100.00
		otbn_dmem_err	12.000s	24.101us	1	1	100.00
V2S	internal_integrity	otbn_alu_bignum_mod_err	1.417m	388.430us	1	1	100.00
		otbn_controller_ispr_rdata_err	7.000s	27.556us	1	1	100.00
		otbn_mac_bignum_acc_err	9.000s	199.475us	1	1	100.00
		otbn_urnd_err	8.000s	76.147us	1	1	100.00
V2S	illegal_bus_access	otbn_illegal_mem_acc	7.000s	12.003us	1	1	100.00
V2S	otbn_mem_gnt_acc_err	otbn_mem_gnt_acc_err	8.000s	15.524us	1	1	100.00
V2S	otbn_non_sec_partial_wipe	otbn_partial_wipe	9.000s	24.941us	1	1	100.00
V2S	tl_intg_err	otbn_sec_cm	1.750m	563.384us	1	1	100.00
		otbn_tl_intg_err	28.000s	491.815us	1	1	100.00
V2S	passthru_mem_tl_intg_err	otbn_passthru_mem_tl_intg_err	14.000s	305.005us	1	1	100.00
V2S	prim_fsm_check	otbn_sec_cm	1.750m	563.384us	1	1	100.00
V2S	prim_count_check	otbn_sec_cm	1.750m	563.384us	1	1	100.00
V2S	sec_cm_mem_scramble	otbn_smoke	12.000s	39.691us	1	1	100.00
V2S	sec_cm_data_mem_integrity	otbn_dmem_err	12.000s	24.101us	1	1	100.00
V2S	sec_cm_instruction_mem_integrity	otbn_imem_err	9.000s	69.154us	1	1	100.00
V2S	sec_cm_bus_integrity	otbn_tl_intg_err	28.000s	491.815us	1	1	100.00
V2S	sec_cm_controller_fsm_global_esc	otbn_escalate	8.000s	21.548us	1	1	100.00
V2S	sec_cm_controller_fsm_local_esc	otbn_imem_err	9.000s	69.154us	1	1	100.00
		otbn_dmem_err	12.000s	24.101us	1	1	100.00
		otbn_zero_state_err_urnd	10.000s	32.912us	1	1	100.00
		otbn_illegal_mem_acc	7.000s	12.003us	1	1	100.00
		otbn_sec_cm	1.750m	563.384us	1	1	100.00
V2S	sec_cm_controller_fsm_sparse	otbn_sec_cm	1.750m	563.384us	1	1	100.00
V2S	sec_cm_scramble_key_sideload	otbn_single	15.000s	77.700us	1	1	100.00
V2S	sec_cm_scramble_ctrl_fsm_local_esc	otbn_imem_err	9.000s	69.154us	1	1	100.00
		otbn_dmem_err	12.000s	24.101us	1	1	100.00
		otbn_zero_state_err_urnd	10.000s	32.912us	1	1	100.00
		otbn_illegal_mem_acc	7.000s	12.003us	1	1	100.00
		otbn_sec_cm	1.750m	563.384us	1	1	100.00
V2S	sec_cm_scramble_ctrl_fsm_sparse	otbn_sec_cm	1.750m	563.384us	1	1	100.00
V2S	sec_cm_start_stop_ctrl_fsm_global_esc	otbn_escalate	8.000s	21.548us	1	1	100.00
V2S	sec_cm_start_stop_ctrl_fsm_local_esc	otbn_imem_err	9.000s	69.154us	1	1	100.00
		otbn_dmem_err	12.000s	24.101us	1	1	100.00
		otbn_zero_state_err_urnd	10.000s	32.912us	1	1	100.00
		otbn_illegal_mem_acc	7.000s	12.003us	1	1	100.00
		otbn_sec_cm	1.750m	563.384us	1	1	100.00
V2S	sec_cm_start_stop_ctrl_fsm_sparse	otbn_sec_cm	1.750m	563.384us	1	1	100.00
V2S	sec_cm_data_reg_sw_sca	otbn_single	15.000s	77.700us	1	1	100.00
V2S	sec_cm_ctrl_redun	otbn_ctrl_redun	9.000s	112.585us	1	1	100.00
V2S	sec_cm_pc_ctrl_flow_redun	otbn_pc_ctrl_flow_redun	11.000s	29.542us	1	1	100.00
V2S	sec_cm_rnd_bus_consistency	otbn_rnd_sec_cm	25.000s	92.843us	1	1	100.00
V2S	sec_cm_rnd_rng_digest	otbn_rnd_sec_cm	25.000s	92.843us	1	1	100.00
V2S	sec_cm_rf_base_data_reg_sw_integrity	otbn_rf_base_intg_err	9.000s	27.740us	1	1	100.00
V2S	sec_cm_rf_base_data_reg_sw_glitch_detect	otbn_sec_cm	1.750m	563.384us	1	1	100.00
V2S	sec_cm_stack_wr_ptr_ctr_redun	otbn_sec_cm	1.750m	563.384us	1	1	100.00
V2S	sec_cm_rf_bignum_data_reg_sw_integrity	otbn_rf_bignum_intg_err	8.000s	332.144us	1	1	100.00
V2S	sec_cm_rf_bignum_data_reg_sw_glitch_detect	otbn_sec_cm	1.750m	563.384us	1	1	100.00
V2S	sec_cm_loop_stack_ctr_redun	otbn_sec_cm	1.750m	563.384us	1	1	100.00
V2S	sec_cm_loop_stack_addr_integrity	otbn_stack_addr_integ_chk	9.000s	51.536us	1	1	100.00
V2S	sec_cm_call_stack_addr_integrity	otbn_stack_addr_integ_chk	9.000s	51.536us	1	1	100.00
V2S	sec_cm_start_stop_ctrl_state_consistency	otbn_sec_wipe_err	8.000s	23.859us	0	1	0.00
V2S	sec_cm_data_mem_sec_wipe	otbn_single	15.000s	77.700us	1	1	100.00
V2S	sec_cm_instruction_mem_sec_wipe	otbn_single	15.000s	77.700us	1	1	100.00
V2S	sec_cm_data_reg_sw_sec_wipe	otbn_single	15.000s	77.700us	1	1	100.00
V2S	sec_cm_write_mem_integrity	otbn_multi	1.117m	386.229us	1	1	100.00
V2S	sec_cm_ctrl_flow_count	otbn_single	15.000s	77.700us	1	1	100.00
V2S	sec_cm_ctrl_flow_sca	otbn_single	15.000s	77.700us	1	1	100.00
V2S	sec_cm_data_mem_sw_noaccess	otbn_sw_no_acc	10.000s	79.454us	1	1	100.00
V2S	sec_cm_key_sideload	otbn_single	15.000s	77.700us	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	otbn_sec_cm	1.750m	563.384us	1	1	100.00
V2S		TOTAL			19	20	95.00
V3	stress_all_with_rand_reset	otbn_stress_all_with_rand_reset	2.950m	793.701us	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			39	41	95.12

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:908) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:

  • Test otbn_stress_all_with_rand_reset has 1 failures.

    • 0.otbn_stress_all_with_rand_reset.90067877085702489930055604914246454018581201915879387771222461085323395133028
      Line 260, in log /nightly/runs/scratch/master/otbn-sim-xcelium/0.otbn_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 793701118 ps: (cip_base_vseq.sv:908) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 793701118 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_dv_otbn_env_*/otbn_insn_cnt_if.sv,21): Assertion InsnCntMatches_A has failed has 1 failures:

  • Test otbn_sec_wipe_err has 1 failures.

    • 0.otbn_sec_wipe_err.1446161558469684020431450021674640069020680791875599926906108742726723936675
      Line 111, in log /nightly/runs/scratch/master/otbn-sim-xcelium/0.otbn_sec_wipe_err/latest/run.log

        xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 23858983 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
        UVM_ERROR @  23858983 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
        UVM_INFO @  23858983 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---