SPI_HOST Simulation Results

Wednesday April 02 2025 17:22:48 UTC

GitHub Revision: 688b340

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke spi_host_smoke 1.250m 11.179ms 1 1 100.00
V1 csr_hw_reset spi_host_csr_hw_reset 3.000s 26.991us 1 1 100.00
V1 csr_rw spi_host_csr_rw 4.000s 21.617us 1 1 100.00
V1 csr_bit_bash spi_host_csr_bit_bash 5.000s 313.340us 1 1 100.00
V1 csr_aliasing spi_host_csr_aliasing 4.000s 50.220us 1 1 100.00
V1 csr_mem_rw_with_rand_reset spi_host_csr_mem_rw_with_rand_reset 3.000s 45.572us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr spi_host_csr_rw 4.000s 21.617us 1 1 100.00
spi_host_csr_aliasing 4.000s 50.220us 1 1 100.00
V1 mem_walk spi_host_mem_walk 3.000s 18.014us 1 1 100.00
V1 mem_partial_access spi_host_mem_partial_access 4.000s 118.573us 1 1 100.00
V1 TOTAL 8 8 100.00
V2 performance spi_host_performance 5.000s 31.994us 1 1 100.00
V2 error_event_intr spi_host_overflow_underflow 8.000s 648.026us 1 1 100.00
spi_host_error_cmd 4.000s 18.492us 1 1 100.00
spi_host_event 3.167m 82.555ms 1 1 100.00
V2 clock_rate spi_host_speed 11.000s 637.308us 1 1 100.00
V2 speed spi_host_speed 11.000s 637.308us 1 1 100.00
V2 chip_select_timing spi_host_speed 11.000s 637.308us 1 1 100.00
V2 sw_reset spi_host_sw_reset 8.000s 185.735us 1 1 100.00
V2 passthrough_mode spi_host_passthrough_mode 5.000s 200.841us 1 1 100.00
V2 cpol_cpha spi_host_speed 11.000s 637.308us 1 1 100.00
V2 full_cycle spi_host_speed 11.000s 637.308us 1 1 100.00
V2 duplex spi_host_smoke 1.250m 11.179ms 1 1 100.00
V2 tx_rx_only spi_host_smoke 1.250m 11.179ms 1 1 100.00
V2 stress_all spi_host_stress_all 6.000s 145.885us 1 1 100.00
V2 spien spi_host_spien 7.000s 471.048us 1 1 100.00
V2 stall spi_host_status_stall 14.000s 1.753ms 1 1 100.00
V2 Idlecsbactive spi_host_idlecsbactive 5.000s 120.427us 1 1 100.00
V2 data_fifo_status spi_host_overflow_underflow 8.000s 648.026us 1 1 100.00
V2 alert_test spi_host_alert_test 4.000s 14.557us 1 1 100.00
V2 intr_test spi_host_intr_test 3.000s 19.984us 1 1 100.00
V2 tl_d_oob_addr_access spi_host_tl_errors 6.000s 130.985us 1 1 100.00
V2 tl_d_illegal_access spi_host_tl_errors 6.000s 130.985us 1 1 100.00
V2 tl_d_outstanding_access spi_host_csr_hw_reset 3.000s 26.991us 1 1 100.00
spi_host_csr_rw 4.000s 21.617us 1 1 100.00
spi_host_csr_aliasing 4.000s 50.220us 1 1 100.00
spi_host_same_csr_outstanding 3.000s 28.921us 1 1 100.00
V2 tl_d_partial_access spi_host_csr_hw_reset 3.000s 26.991us 1 1 100.00
spi_host_csr_rw 4.000s 21.617us 1 1 100.00
spi_host_csr_aliasing 4.000s 50.220us 1 1 100.00
spi_host_same_csr_outstanding 3.000s 28.921us 1 1 100.00
V2 TOTAL 15 15 100.00
V2S tl_intg_err spi_host_tl_intg_err 5.000s 152.504us 1 1 100.00
spi_host_sec_cm 5.000s 267.086us 1 1 100.00
V2S sec_cm_bus_integrity spi_host_tl_intg_err 5.000s 152.504us 1 1 100.00
V2S TOTAL 2 2 100.00
Unmapped tests spi_host_upper_range_clkdiv 0 1 0.00
TOTAL 25 26 96.15

Failure Buckets