UART Simulation Results

Wednesday April 02 2025 17:22:48 UTC

GitHub Revision: 688b340

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	4.150s	663.383us	1	1	100.00
V1	csr_hw_reset	uart_csr_hw_reset	1.600s	22.779us	1	1	100.00
V1	csr_rw	uart_csr_rw	1.580s	19.650us	1	1	100.00
V1	csr_bit_bash	uart_csr_bit_bash	2.450s	181.210us	1	1	100.00
V1	csr_aliasing	uart_csr_aliasing	1.960s	307.414us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	1.610s	26.616us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	1.580s	19.650us	1	1	100.00
		uart_csr_aliasing	1.960s	307.414us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	base_random_seq	uart_tx_rx	11.980s	27.900ms	1	1	100.00
V2	parity	uart_smoke	4.150s	663.383us	1	1	100.00
		uart_tx_rx	11.980s	27.900ms	1	1	100.00
V2	parity_error	uart_intr	41.950s	38.339ms	1	1	100.00
		uart_rx_parity_err	5.590s	7.427ms	1	1	100.00
V2	watermark	uart_tx_rx	11.980s	27.900ms	1	1	100.00
		uart_intr	41.950s	38.339ms	1	1	100.00
V2	fifo_full	uart_fifo_full	2.125m	294.445ms	1	1	100.00
V2	fifo_overflow	uart_fifo_overflow	1.146m	61.033ms	1	1	100.00
V2	fifo_reset	uart_fifo_reset	32.450s	63.419ms	1	1	100.00
V2	rx_frame_err	uart_intr	41.950s	38.339ms	1	1	100.00
V2	rx_break_err	uart_intr	41.950s	38.339ms	1	1	100.00
V2	rx_timeout	uart_intr	41.950s	38.339ms	1	1	100.00
V2	perf	uart_perf	2.389m	15.368ms	1	1	100.00
V2	sys_loopback	uart_loopback	8.370s	5.849ms	1	1	100.00
V2	line_loopback	uart_loopback	8.370s	5.849ms	1	1	100.00
V2	rx_noise_filter	uart_noise_filter	19.930s	57.247ms	1	1	100.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	3.700s	2.033ms	1	1	100.00
V2	tx_overide	uart_tx_ovrd	10.860s	6.252ms	1	1	100.00
V2	rx_oversample	uart_rx_oversample	13.580s	7.071ms	1	1	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	55.650s	60.260ms	1	1	100.00
V2	stress_all	uart_stress_all	2.211m	118.624ms	1	1	100.00
V2	alert_test	uart_alert_test	1.630s	12.772us	1	1	100.00
V2	intr_test	uart_intr_test	1.390s	21.172us	1	1	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	1.860s	100.865us	1	1	100.00
V2	tl_d_illegal_access	uart_tl_errors	1.860s	100.865us	1	1	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	1.600s	22.779us	1	1	100.00
		uart_csr_rw	1.580s	19.650us	1	1	100.00
		uart_csr_aliasing	1.960s	307.414us	1	1	100.00
		uart_same_csr_outstanding	1.550s	37.426us	1	1	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	1.600s	22.779us	1	1	100.00
		uart_csr_rw	1.580s	19.650us	1	1	100.00
		uart_csr_aliasing	1.960s	307.414us	1	1	100.00
		uart_same_csr_outstanding	1.550s	37.426us	1	1	100.00
V2		TOTAL			18	18	100.00
V2S	tl_intg_err	uart_sec_cm	1.790s	334.053us	1	1	100.00
		uart_tl_intg_err	2.040s	96.547us	1	1	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	2.040s	96.547us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	46.240s	8.586ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			27	27	100.00