CHIP Simulation Results

Wednesday April 02 2025 17:22:48 UTC

GitHub Revision: `688b340`

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	chip_sw_uart_tx_rx	chip_sw_uart_tx_rx	1.052m		0	1	0.00
V1	chip_sw_uart_rx_overflow	chip_sw_uart_tx_rx	1.052m		0	1	0.00
V1	chip_sw_uart_rand_baudrate	chip_sw_uart_rand_baudrate	16.054s		0	1	0.00
V1	chip_sw_uart_tx_rx_alt_clk_freq	chip_sw_uart_tx_rx_alt_clk_freq	16.065s		0	1	0.00
		chip_sw_uart_tx_rx_alt_clk_freq_low_speed	1.282m		0	1	0.00
V1	chip_sw_gpio_out	chip_sw_gpio	6.657m	6.585ms	1	1	100.00
V1	chip_sw_gpio_in	chip_sw_gpio	6.657m	6.585ms	1	1	100.00
V1	chip_sw_gpio_irq	chip_sw_gpio	6.657m	6.585ms	1	1	100.00
V1	chip_sw_example_tests	chip_sw_example_rom	1.270m		0	1	0.00
		chip_sw_example_manufacturer	1.304m		0	1	0.00
		chip_sw_example_concurrency	3.673m	3.672ms	1	1	100.00
		chip_sw_uart_smoketest_signed	30.130s		0	1	0.00
V1	csr_bit_bash	chip_csr_bit_bash	9.710s		0	1	0.00
V1	csr_aliasing	chip_csr_aliasing	10.040s		0	1	0.00
V1	regwen_csr_and_corresponding_lockable_csr	chip_csr_aliasing	10.040s		0	1	0.00
V1	xbar_smoke	xbar_smoke	11.340s	12.736us	1	1	100.00
V1		TOTAL			3	12	25.00
V2	chip_sw_spi_device_flash_mode	chip_sw_uart_tx_rx_bootstrap	52.107s		0	1	0.00
V2	chip_sw_spi_device_pass_through	chip_sw_spi_device_pass_through	10.699m	8.924ms	1	1	100.00
V2	chip_sw_spi_device_pass_through_collision	chip_sw_spi_device_pass_through_collision	4.584m	6.247ms	0	1	0.00
V2	chip_sw_spi_device_tpm	chip_sw_spi_device_tpm	1.349m		0	1	0.00
V2	chip_sw_spi_host_tx_rx	chip_sw_spi_host_tx_rx	1.181m		0	1	0.00
V2	chip_sw_i2c_host_tx_rx	chip_sw_i2c_host_tx_rx	1.298m		0	1	0.00
V2	chip_sw_i2c_device_tx_rx	chip_sw_i2c_device_tx_rx	1.181m		0	1	0.00
V2	chip_pin_mux	chip_padctrl_attributes	3.450s		0	1	0.00
V2	chip_padctrl_attributes	chip_padctrl_attributes	3.450s		0	1	0.00
V2	chip_sw_sleep_pin_wake	chip_sw_sleep_pin_wake	2.920m		0	1	0.00
V2	chip_sw_sleep_pin_retention	chip_sw_sleep_pin_retention	1.102m		0	1	0.00
V2	chip_sw_data_integrity	chip_sw_data_integrity_escalation	1.136m		0	1	0.00
V2	chip_sw_instruction_integrity	chip_sw_data_integrity_escalation	1.136m		0	1	0.00
V2	chip_jtag_csr_rw	chip_jtag_csr_rw	2.581m	4.232ms	0	1	0.00
V2	chip_jtag_mem_access	chip_jtag_mem_access	3.731m	4.384ms	0	1	0.00
V2	chip_rv_dm_ndm_reset_req	chip_rv_dm_ndm_reset_req	5.163m	6.832ms	1	1	100.00
V2	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	12.036s		0	1	0.00
V2	chip_rv_dm_access_after_wakeup	chip_sw_rv_dm_access_after_wakeup	13.046s		0	1	0.00
V2	chip_rv_dm_lc_disabled	chip_rv_dm_lc_disabled	18.466m	25.739ms	1	1	100.00
V2	chip_sw_timer	chip_sw_rv_timer_irq	5.128m	5.278ms	1	1	100.00
V2	chip_sw_aon_timer_wakeup_irq	chip_sw_aon_timer_irq	22.584m	18.016ms	0	1	0.00
V2	chip_sw_aon_timer_wdog_bark_irq	chip_sw_aon_timer_irq	22.584m	18.016ms	0	1	0.00
V2	chip_sw_aon_timer_wdog_lc_escalate	chip_sw_aon_timer_wdog_lc_escalate	13.088s		0	1	0.00
V2	chip_sw_aon_timer_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	14.077s		0	1	0.00
V2	chip_sw_aon_timer_sleep_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	14.077s		0	1	0.00
V2	chip_sw_aon_timer_sleep_wdog_sleep_pause	chip_sw_aon_timer_sleep_wdog_sleep_pause	19.015s		0	1	0.00
V2	chip_sw_plic_all_irqs	chip_plic_all_irqs	14.064s		0	1	0.00
V2	chip_sw_plic_sw_irq	chip_sw_plic_sw_irq	3.888m	4.465ms	1	1	100.00
V2	chip_sw_clkmgr_idle_trans	chip_sw_otbn_randomness	4.755m	5.101ms	1	1	100.00
		chip_sw_aes_idle	3.772m	5.362ms	1	1	100.00
		chip_sw_hmac_enc_idle	4.638m	5.362ms	1	1	100.00
		chip_sw_kmac_idle	3.447m	4.236ms	1	1	100.00
V2	chip_sw_clkmgr_off_trans	chip_sw_clkmgr_off_aes_trans	12.057s		0	1	0.00
		chip_sw_clkmgr_off_hmac_trans	12.066s		0	1	0.00
		chip_sw_clkmgr_off_kmac_trans	11.059s		0	1	0.00
		chip_sw_clkmgr_off_otbn_trans	13.064s		0	1	0.00
V2	chip_sw_clkmgr_div	chip_sw_clkmgr_external_clk_src_for_lc	12.059s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	12.056s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	13.071s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	12.063s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	11.053s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	11.051s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	11.065s		0	1	0.00
V2	chip_sw_clkmgr_external_clk_src_for_lc	chip_sw_clkmgr_external_clk_src_for_lc	12.059s		0	1	0.00
V2	chip_sw_clkmgr_external_clk_src_for_sw	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	12.056s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	13.071s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	12.063s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	11.053s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	11.051s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	11.065s		0	1	0.00
V2	chip_sw_clkmgr_jitter	chip_sw_otbn_ecdsa_op_irq_jitter_en	14.033s		0	1	0.00
		chip_sw_aes_enc_jitter_en	48.040s	10.340us	0	1	0.00
		chip_sw_hmac_enc_jitter_en	46.240s	10.320us	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	45.330s	10.180us	0	1	0.00
		chip_sw_kmac_mode_kmac_jitter_en	44.950s	10.140us	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	12.051s		0	1	0.00
		chip_sw_clkmgr_jitter	3.844m	5.404ms	1	1	100.00
V2	chip_sw_clkmgr_extended_range	chip_sw_clkmgr_jitter_reduced_freq	3.922m	4.438ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq	14.039s		0	1	0.00
		chip_sw_aes_enc_jitter_en_reduced_freq	1.044m	10.200us	0	1	0.00
		chip_sw_hmac_enc_jitter_en_reduced_freq	47.000s	10.220us	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en_reduced_freq	45.060s	10.140us	0	1	0.00
		chip_sw_kmac_mode_kmac_jitter_en_reduced_freq	45.580s	10.200us	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq	58.730s	10.340us	0	1	0.00
		chip_sw_csrng_edn_concurrency_reduced_freq	14.050s		0	1	0.00
V2	chip_sw_clkmgr_deep_sleep_frequency	chip_sw_ast_clk_outputs	13.049s		0	1	0.00
V2	chip_sw_clkmgr_sleep_frequency	chip_sw_clkmgr_sleep_frequency	11.055s		0	1	0.00
V2	chip_sw_clkmgr_reset_frequency	chip_sw_clkmgr_reset_frequency	11.062s		0	1	0.00
V2	chip_sw_clkmgr_escalation_reset	chip_sw_all_escalation_resets	19.771m	13.116ms	1	1	100.00
V2	chip_sw_pwrmgr_external_full_reset	chip_sw_pwrmgr_full_aon_reset	8.212m	12.507ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_all_reset_reqs	chip_sw_aon_timer_wdog_bite_reset	14.077s		0	1	0.00
V2	chip_sw_pwrmgr_wdog_reset	chip_sw_pwrmgr_wdog_reset	12.083s		0	1	0.00
V2	chip_sw_pwrmgr_aon_power_glitch_reset	chip_sw_pwrmgr_full_aon_reset	8.212m	12.507ms	1	1	100.00
V2	chip_sw_pwrmgr_main_power_glitch_reset	chip_sw_pwrmgr_main_power_glitch_reset	19.044s		0	1	0.00
V2	chip_sw_pwrmgr_random_sleep_power_glitch_reset	chip_sw_pwrmgr_random_sleep_power_glitch_reset	23.045s		0	1	0.00
V2	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	19.038s		0	1	0.00
V2	chip_sw_pwrmgr_sleep_power_glitch_reset	chip_sw_pwrmgr_sleep_power_glitch_reset	23.052s		0	1	0.00
V2	chip_sw_pwrmgr_sleep_disabled	chip_sw_pwrmgr_sleep_disabled	13.035s		0	1	0.00
V2	chip_sw_pwrmgr_escalation_reset	chip_sw_all_escalation_resets	19.771m	13.116ms	1	1	100.00
V2	chip_sw_rstmgr_sys_reset_info	chip_rv_dm_ndm_reset_req	5.163m	6.832ms	1	1	100.00
V2	chip_sw_rstmgr_cpu_info	chip_sw_rstmgr_cpu_info	5.760m	20.025ms	0	1	0.00
V2	chip_sw_rstmgr_sw_req_reset	chip_sw_rstmgr_sw_req	5.375m	5.742ms	1	1	100.00
V2	chip_sw_rstmgr_alert_info	chip_sw_rstmgr_alert_info	18.627m	30.017ms	0	1	0.00
V2	chip_sw_rstmgr_sw_rst	chip_sw_rstmgr_sw_rst	4.175m	4.409ms	1	1	100.00
V2	chip_sw_rstmgr_escalation_reset	chip_sw_all_escalation_resets	19.771m	13.116ms	1	1	100.00
V2	chip_sw_alert_handler_alerts	chip_sw_alert_test	15.013s		0	1	0.00
V2	chip_sw_alert_handler_escalations	chip_sw_alert_handler_escalation	12.031s		0	1	0.00
V2	chip_sw_all_escalation_resets	chip_sw_all_escalation_resets	19.771m	13.116ms	1	1	100.00
V2	chip_sw_alert_handler_irqs	chip_plic_all_irqs	14.064s		0	1	0.00
V2	chip_sw_alert_handler_entropy	chip_sw_alert_handler_entropy	12.073s		0	1	0.00
V2	chip_sw_alert_handler_crashdump	chip_sw_rstmgr_alert_info	18.627m	30.017ms	0	1	0.00
V2	chip_sw_alert_handler_ping_timeout	chip_sw_alert_handler_ping_timeout	16.089s		0	1	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_alerts	chip_sw_alert_handler_lpg_sleep_mode_alerts	14.089s		0	1	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_pings	chip_sw_alert_handler_lpg_sleep_mode_pings	12.091s		0	1	0.00
V2	chip_sw_alert_handler_lpg_clock_off	chip_sw_alert_handler_lpg_clkoff	12.080s		0	1	0.00
V2	chip_sw_alert_handler_lpg_reset_toggle	chip_sw_alert_handler_lpg_reset_toggle	12.077s		0	1	0.00
V2	chip_sw_alert_handler_reverse_ping_in_deep_sleep	chip_sw_alert_handler_reverse_ping_in_deep_sleep	12.067s		0	1	0.00
V2	chip_sw_lc_ctrl_alert_handler_escalation	chip_sw_alert_handler_escalation	12.031s		0	1	0.00
V2	chip_sw_lc_ctrl_jtag_access	chip_sw_lc_ctrl_transition	12.098s		0	1	0.00
V2	chip_sw_lc_ctrl_otp_hw_cfg	chip_sw_lc_ctrl_otp_hw_cfg	1.264m		0	1	0.00
V2	chip_sw_lc_ctrl_init	chip_sw_lc_ctrl_transition	12.098s		0	1	0.00
V2	chip_sw_lc_ctrl_transitions	chip_sw_lc_ctrl_transition	12.098s		0	1	0.00
V2	chip_sw_lc_ctrl_kmac_req	chip_sw_lc_ctrl_transition	12.098s		0	1	0.00
V2	chip_sw_lc_ctrl_key_div	chip_sw_keymgr_dpe_key_derivation_prod	8.121m	20.010ms	0	1	0.00
V2	chip_sw_lc_ctrl_broadcast	chip_sw_otp_ctrl_lc_signals_test_unlocked0	1.180m		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_dev	39.656s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_prod	41.436s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_rma	1.036m		0	1	0.00
		chip_sw_lc_ctrl_transition	12.098s		0	1	0.00
		chip_sw_keymgr_dpe_key_derivation	7.309m	7.624ms	0	1	0.00
		chip_sw_rom_ctrl_integrity_check	8.847m	12.932ms	1	1	100.00
		chip_sw_sram_ctrl_execution_main	12.060s		0	1	0.00
		chip_prim_tl_access	9.492m	14.365ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_lc	12.059s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	12.056s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	13.071s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	12.063s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	11.053s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	11.051s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	11.065s		0	1	0.00
		chip_rv_dm_lc_disabled	18.466m	25.739ms	1	1	100.00
V2	chip_sw_aes_enc	chip_sw_aes_enc	4.306m	4.446ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	48.040s	10.340us	0	1	0.00
V2	chip_sw_aes_entropy	chip_sw_aes_entropy	3.972m	4.878ms	1	1	100.00
V2	chip_sw_aes_idle	chip_sw_aes_idle	3.772m	5.362ms	1	1	100.00
V2	chip_sw_hmac_enc	chip_sw_hmac_enc	3.950m	4.674ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	46.240s	10.320us	0	1	0.00
V2	chip_sw_hmac_idle	chip_sw_hmac_enc_idle	4.638m	5.362ms	1	1	100.00
V2	chip_sw_kmac_enc	chip_sw_kmac_mode_cshake	5.232m	5.932ms	1	1	100.00
		chip_sw_kmac_mode_kmac	5.679m	5.792ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	44.950s	10.140us	0	1	0.00
V2	chip_sw_kmac_app_keymgr	chip_sw_keymgr_dpe_key_derivation	7.309m	7.624ms	0	1	0.00
V2	chip_sw_kmac_app_lc	chip_sw_lc_ctrl_transition	12.098s		0	1	0.00
V2	chip_sw_kmac_app_rom	chip_sw_kmac_app_rom	37.160s	10.200us	0	1	0.00
V2	chip_sw_kmac_entropy	chip_sw_kmac_entropy	4.708m	4.224ms	1	1	100.00
V2	chip_sw_kmac_idle	chip_sw_kmac_idle	3.447m	4.236ms	1	1	100.00
V2	chip_sw_entropy_src_csrng	chip_sw_entropy_src_csrng	15.075s		0	1	0.00
V2	chip_sw_csrng_edn_cmd	chip_sw_entropy_src_csrng	15.075s		0	1	0.00
V2	chip_sw_csrng_fuse_en_sw_app_read	chip_sw_csrng_fuse_en_sw_app_read_test	12.068s		0	1	0.00
V2	chip_sw_csrng_known_answer_tests	chip_sw_csrng_kat_test	4.377m	4.212ms	1	1	100.00
V2	chip_sw_edn_entropy_reqs	chip_sw_csrng_edn_concurrency	13.071s		0	1	0.00
V2	chip_sw_keymgr_dpe_key_derivation	chip_sw_keymgr_dpe_key_derivation	7.309m	7.624ms	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	45.330s	10.180us	0	1	0.00
V2	chip_sw_otbn_op	chip_sw_otbn_ecdsa_op_irq	14.035s		0	1	0.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	14.033s		0	1	0.00
V2	chip_sw_otbn_rnd_entropy	chip_sw_otbn_randomness	4.755m	5.101ms	1	1	100.00
V2	chip_sw_otbn_urnd_entropy	chip_sw_otbn_randomness	4.755m	5.101ms	1	1	100.00
V2	chip_sw_otbn_idle	chip_sw_otbn_randomness	4.755m	5.101ms	1	1	100.00
V2	chip_sw_otbn_mem_scramble	chip_sw_otbn_mem_scramble	7.346m	5.288ms	1	1	100.00
V2	chip_sw_rom_access	chip_sw_rom_ctrl_integrity_check	8.847m	12.932ms	1	1	100.00
V2	chip_sw_rom_ctrl_integrity_check	chip_sw_rom_ctrl_integrity_check	8.847m	12.932ms	1	1	100.00
V2	chip_sw_sram_scrambled_access	chip_sw_sram_ctrl_scrambled_access	14.043s		0	1	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	12.051s		0	1	0.00
V2	chip_sw_sram_execution	chip_sw_sram_ctrl_execution_main	12.060s		0	1	0.00
V2	chip_sw_sram_lc_escalation	chip_sw_all_escalation_resets	19.771m	13.116ms	1	1	100.00
		chip_sw_data_integrity_escalation	1.136m		0	1	0.00
V2	chip_otp_ctrl_init	chip_sw_lc_ctrl_transition	12.098s		0	1	0.00
V2	chip_sw_otp_ctrl_keys	chip_sw_otbn_mem_scramble	7.346m	5.288ms	1	1	100.00
		chip_sw_keymgr_dpe_key_derivation	7.309m	7.624ms	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access	14.043s		0	1	0.00
		chip_sw_rv_core_ibex_icache_invalidate	4.248m	5.617ms	1	1	100.00
V2	chip_sw_otp_ctrl_entropy	chip_sw_otbn_mem_scramble	7.346m	5.288ms	1	1	100.00
		chip_sw_keymgr_dpe_key_derivation	7.309m	7.624ms	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access	14.043s		0	1	0.00
		chip_sw_rv_core_ibex_icache_invalidate	4.248m	5.617ms	1	1	100.00
V2	chip_sw_otp_ctrl_program	chip_sw_lc_ctrl_transition	12.098s		0	1	0.00
V2	chip_sw_otp_ctrl_program_error	chip_sw_lc_ctrl_program_error	12.035s		0	1	0.00
V2	chip_sw_otp_ctrl_hw_cfg	chip_sw_lc_ctrl_otp_hw_cfg	1.264m		0	1	0.00
V2	chip_sw_otp_ctrl_lc_signals	chip_sw_otp_ctrl_lc_signals_test_unlocked0	1.180m		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_dev	39.656s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_prod	41.436s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_rma	1.036m		0	1	0.00
		chip_sw_lc_ctrl_transition	12.098s		0	1	0.00
		chip_prim_tl_access	9.492m	14.365ms	1	1	100.00
V2	chip_sw_otp_prim_tl_access	chip_prim_tl_access	9.492m	14.365ms	1	1	100.00
V2	chip_sw_otp_ctrl_nvm_cnt	chip_sw_otp_ctrl_nvm_cnt	12.093s		0	1	0.00
V2	chip_sw_otp_ctrl_sw_parts	chip_sw_otp_ctrl_sw_parts	17.108s		0	1	0.00
V2	chip_sw_ast_clk_outputs	chip_sw_ast_clk_outputs	13.049s		0	1	0.00
V2	chip_sw_ast_sys_clk_jitter	chip_sw_otbn_ecdsa_op_irq_jitter_en	14.033s		0	1	0.00
		chip_sw_aes_enc_jitter_en	48.040s	10.340us	0	1	0.00
		chip_sw_hmac_enc_jitter_en	46.240s	10.320us	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	45.330s	10.180us	0	1	0.00
		chip_sw_kmac_mode_kmac_jitter_en	44.950s	10.140us	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	12.051s		0	1	0.00
		chip_sw_clkmgr_jitter	3.844m	5.404ms	1	1	100.00
V2	chip_sw_soc_proxy_external_reset_requests	chip_sw_soc_proxy_smoketest	7.870m	5.974ms	1	1	100.00
V2	chip_sw_soc_proxy_external_irqs	chip_sw_soc_proxy_smoketest	7.870m	5.974ms	1	1	100.00
V2	chip_sw_soc_proxy_external_alerts	chip_sw_soc_proxy_external_alerts	3.975m	4.451ms	0	1	0.00
V2	chip_sw_soc_proxy_external_wakeup_requests	chip_sw_soc_proxy_external_wakeup	5.153m	5.280ms	1	1	100.00
V2	chip_sw_soc_proxy_gpios	chip_sw_soc_proxy_gpios	3.548m	5.441ms	1	1	100.00
V2	chip_sw_nmi_irq	chip_sw_rv_core_ibex_nmi_irq	6.503m	5.029ms	0	1	0.00
V2	chip_sw_rv_core_ibex_rnd	chip_sw_rv_core_ibex_rnd	4.768m	4.352ms	1	1	100.00
V2	chip_sw_rv_core_ibex_address_translation	chip_sw_rv_core_ibex_address_translation	4.210m	4.831ms	1	1	100.00
V2	chip_sw_rv_core_ibex_icache_scrambled_access	chip_sw_rv_core_ibex_icache_invalidate	4.248m	5.617ms	1	1	100.00
V2	chip_sw_rv_core_ibex_fault_dump	chip_sw_rstmgr_cpu_info	5.760m	20.025ms	0	1	0.00
V2	chip_sw_rv_core_ibex_double_fault	chip_sw_rstmgr_cpu_info	5.760m	20.025ms	0	1	0.00
V2	chip_sw_smoketest	chip_sw_aes_smoketest	3.184m	4.135ms	1	1	100.00
		chip_sw_aon_timer_smoketest	3.132m	3.744ms	1	1	100.00
		chip_sw_clkmgr_smoketest	2.890m	4.536ms	1	1	100.00
		chip_sw_csrng_smoketest	3.358m	4.221ms	1	1	100.00
		chip_sw_gpio_smoketest	3.588m	4.127ms	1	1	100.00
		chip_sw_hmac_smoketest	4.083m	5.051ms	1	1	100.00
		chip_sw_kmac_smoketest	4.132m	4.930ms	1	1	100.00
		chip_sw_otbn_smoketest	4.891m	5.245ms	1	1	100.00
		chip_sw_otp_ctrl_smoketest	3.022m	4.019ms	1	1	100.00
		chip_sw_rv_plic_smoketest	3.023m	4.012ms	1	1	100.00
		chip_sw_rv_timer_smoketest	4.979m	4.874ms	1	1	100.00
		chip_sw_rstmgr_smoketest	3.071m	4.928ms	1	1	100.00
		chip_sw_sram_ctrl_smoketest	3.044m	4.092ms	1	1	100.00
		chip_sw_uart_smoketest	3.879m	5.366ms	1	1	100.00
V2	chip_sw_rom_functests	rom_keymgr_functest	18.103s		0	1	0.00
V2	chip_sw_signed	chip_sw_uart_smoketest_signed	30.130s		0	1	0.00
V2	chip_sw_boot	chip_sw_uart_tx_rx_bootstrap	52.107s		0	1	0.00
V2	chip_sw_secure_boot	base_rom_e2e_smoke	15.044s		0	1	0.00
V2	chip_lc_scrap	chip_sw_lc_ctrl_rma_to_scrap	3.703m	3.698ms	1	1	100.00
		chip_sw_lc_ctrl_raw_to_scrap	4.210m	4.829ms	1	1	100.00
		chip_sw_lc_ctrl_test_locked0_to_scrap	38.405m	60.000ms	0	1	0.00
		chip_sw_lc_ctrl_rand_to_scrap	3.884m	5.546ms	1	1	100.00
V2	chip_lc_test_locked	chip_sw_lc_walkthrough_testunlocks	17.055s		0	1	0.00
		chip_rv_dm_lc_disabled	18.466m	25.739ms	1	1	100.00
V2	chip_sw_lc_walkthrough	chip_sw_lc_walkthrough_dev	13.058s		0	1	0.00
		chip_sw_lc_walkthrough_prod	18.064s		0	1	0.00
		chip_sw_lc_walkthrough_prodend	20.072s		0	1	0.00
		chip_sw_lc_walkthrough_rma	17.055s		0	1	0.00
		chip_sw_lc_walkthrough_testunlocks	17.055s		0	1	0.00
V2	chip_sw_lc_ctrl_volatile_raw_unlock	chip_sw_lc_ctrl_volatile_raw_unlock	26.094s		0	1	0.00
		chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	36.101s		0	1	0.00
		rom_volatile_raw_unlock	11.112s		0	1	0.00
V2	chip_sw_rom_raw_unlock	rom_raw_unlock	11.115s		0	1	0.00
V2	chip_sw_exit_test_unlocked_bootstrap	chip_sw_exit_test_unlocked_bootstrap	22.070s		0	1	0.00
V2	chip_sw_inject_scramble_seed	chip_sw_inject_scramble_seed	35.123s		0	1	0.00
V2	tl_d_oob_addr_access	chip_tl_errors	3.167m	3.702ms	0	1	0.00
V2	tl_d_illegal_access	chip_tl_errors	3.167m	3.702ms	0	1	0.00
V2	tl_d_outstanding_access	chip_csr_aliasing	10.040s		0	1	0.00
		chip_same_csr_outstanding	9.280s		0	1	0.00
V2	tl_d_partial_access	chip_csr_aliasing	10.040s		0	1	0.00
		chip_same_csr_outstanding	9.280s		0	1	0.00
V2	xbar_base_random_sequence	xbar_random	12.030s	12.251us	1	1	100.00
V2	xbar_random_delay	xbar_smoke_zero_delays	8.540s	11.724us	1	1	100.00
		xbar_smoke_large_delays	4.859m	2.621ms	1	1	100.00
		xbar_smoke_slow_rsp	4.831m	1.845ms	1	1	100.00
		xbar_random_zero_delays	1.260m	70.094us	1	1	100.00
		xbar_random_large_delays	16.962m	8.751ms	1	1	100.00
		xbar_random_slow_rsp	9.685m	3.632ms	1	1	100.00
V2	xbar_unmapped_address	xbar_unmapped_addr	57.210s	40.955us	1	1	100.00
		xbar_error_and_unmapped_addr	53.800s	44.356us	1	1	100.00
V2	xbar_error_cases	xbar_error_random	1.572m	315.192us	1	1	100.00
		xbar_error_and_unmapped_addr	53.800s	44.356us	1	1	100.00
V2	xbar_all_access_same_device	xbar_access_same_device	3.185m	580.259us	1	1	100.00
		xbar_access_same_device_slow_rsp	11.781m	4.272ms	1	1	100.00
V2	xbar_all_hosts_use_same_source_id	xbar_same_source	1.937m	350.006us	1	1	100.00
V2	xbar_stress_all	xbar_stress_all	2.900m	133.065us	1	1	100.00
		xbar_stress_all_with_error	6.984m	428.471us	1	1	100.00
V2	xbar_stress_with_reset	xbar_stress_all_with_rand_reset	20.248m	803.616us	1	1	100.00
		xbar_stress_all_with_reset_error	22.119m	2.629ms	1	1	100.00
V2	rom_e2e_smoke	rom_e2e_smoke	13.022s		0	1	0.00
V2	rom_e2e_shutdown_output	rom_e2e_shutdown_output	13.050s		0	1	0.00
V2	rom_e2e_shutdown_exception_c	rom_e2e_shutdown_exception_c	14.050s		0	1	0.00
V2	rom_e2e_boot_policy_valid	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	12.039s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_dev	12.035s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod	12.048s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod_end	13.075s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_rma	13.095s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	12.074s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_dev	13.086s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod	13.088s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	11.052s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_rma	12.073s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	14.084s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_dev	13.078s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod	12.081s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	12.079s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_rma	13.083s		0	1	0.00
V2	rom_e2e_sigverify_always	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	14.101s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_dev	13.076s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod	14.101s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod_end	12.064s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_rma	13.081s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	13.095s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_dev	13.146s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod	12.132s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	13.140s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_rma	12.134s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	13.139s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_dev	14.147s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod	13.128s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	12.119s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_rma	14.132s		0	1	0.00
V2	rom_e2e_asm_init	rom_e2e_asm_init_test_unlocked0	13.126s		0	1	0.00
		rom_e2e_asm_init_dev	13.130s		0	1	0.00
		rom_e2e_asm_init_prod	13.093s		0	1	0.00
		rom_e2e_asm_init_prod_end	12.092s		0	1	0.00
		rom_e2e_asm_init_rma	12.092s		0	1	0.00
V2	rom_e2e_keymgr_init	rom_e2e_keymgr_init_rom_ext_meas	11.087s		0	1	0.00
		rom_e2e_keymgr_init_rom_ext_no_meas	12.095s		0	1	0.00
		rom_e2e_keymgr_init_rom_ext_invalid_meas	12.105s		0	1	0.00
V2	rom_e2e_static_critical	rom_e2e_static_critical	12.100s		0	1	0.00
V2		TOTAL			65	206	31.55
V2S	chip_sw_aes_masking_off	chip_sw_aes_masking_off	4.141m	5.030ms	1	1	100.00
V2S	chip_sw_rv_core_ibex_lockstep_glitch	chip_sw_rv_core_ibex_lockstep_glitch	3.401m	4.161ms	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	chip_rv_dm_perform_debug	rom_e2e_jtag_debug_test_unlocked0	11.084s		0	1	0.00
		rom_e2e_jtag_debug_dev	12.092s		0	1	0.00
		rom_e2e_jtag_debug_rma	12.092s		0	1	0.00
V3	chip_sw_rv_dm_access_after_hw_reset	chip_sw_rv_dm_access_after_escalation_reset	15.058s		0	1	0.00
V3	chip_sw_plic_alerts	chip_sw_all_escalation_resets	19.771m	13.116ms	1	1	100.00
V3	chip_sw_otp_ctrl_vendor_test_csr_access	chip_sw_otp_ctrl_vendor_test_csr_access	13.063s		0	1	0.00
V3	chip_sw_otp_ctrl_escalation	chip_sw_otp_ctrl_escalation	15.613m	13.963ms	1	1	100.00
V3	chip_sw_coremark	chip_sw_coremark	11.057s		0	1	0.00
V3	chip_sw_power_max_load	chip_sw_power_virus	12.026s		0	1	0.00
V3	rom_e2e_debug	rom_e2e_jtag_debug_test_unlocked0	11.084s		0	1	0.00
		rom_e2e_jtag_debug_dev	12.092s		0	1	0.00
		rom_e2e_jtag_debug_rma	12.092s		0	1	0.00
V3	rom_e2e_jtag_inject	rom_e2e_jtag_inject_test_unlocked0	11.085s		0	1	0.00
		rom_e2e_jtag_inject_dev	11.083s		0	1	0.00
		rom_e2e_jtag_inject_rma	11.094s		0	1	0.00
V3	rom_e2e_self_hash	rom_e2e_self_hash	1.421m		0	1	0.00
V3		TOTAL			1	12	8.33
	Unmapped tests	chip_sw_rstmgr_rst_cnsty_escalation	17.876m	17.643ms	0	1	0.00
		chip_sw_dma_inline_hashing	3.839m	4.505ms	1	1	100.00
		chip_sw_dma_abort	4.366m	4.358ms	0	1	0.00
		rom_e2e_sigverify_mod_exp_test_unlocked0_otbn	12.105s		0	1	0.00
		rom_e2e_sigverify_mod_exp_test_unlocked0_sw	11.097s		0	1	0.00
		rom_e2e_sigverify_mod_exp_dev_otbn	12.105s		0	1	0.00
		rom_e2e_sigverify_mod_exp_dev_sw	12.108s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_otbn	11.113s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_sw	12.124s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_end_otbn	11.104s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_end_sw	11.113s		0	1	0.00
		rom_e2e_sigverify_mod_exp_rma_otbn	12.118s		0	1	0.00
		rom_e2e_sigverify_mod_exp_rma_sw	12.118s		0	1	0.00
		chip_sw_mbx_smoketest	3.540m	4.008ms	1	1	100.00
		TOTAL			73	246	29.67

Failure Buckets

Job returned non-zero exit code has 145 failures:

Test chip_sw_example_rom has 1 failures.

0.chip_sw_example_rom.58439426962669940521785311662494718482093740905483655546150153510454508065262
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_example_rom/latest/run.log

  Target //sw/device/tests:example_test_from_rom_sim_dv failed to build
  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests:example_test_from_rom_sim_dv' failed; build aborted: Target //sw/device/tests:example_test_from_rom_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests:example_test_from_rom_sim_dv (109628)
      //hw/top_earlgrey/sw/autogen:top_earlgrey (8da0bf)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 65.336s, Critical Path: 0.05s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_example_manufacturer has 1 failures.

0.chip_sw_example_manufacturer.66690275252103118586005016697800996105655310855778037675481941601570640937877
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_example_manufacturer/latest/run.log

  Analyzing: target @@+hooks+manufacturer_test_hooks//:example_test_sim_dv (1 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '@@+hooks+manufacturer_test_hooks//:example_test_sim_dv' failed; build aborted: Target @@+hooks+manufacturer_test_hooks//:example_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      @@+hooks+manufacturer_test_hooks//:example_test_sim_dv (8822ab)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 66.146s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_data_integrity_escalation has 1 failures.

0.chip_sw_data_integrity_escalation.97901589845470496228740732459722165400873098055067750662714574696995845724978
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_data_integrity_escalation/latest/run.log

  Analyzing: target //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv (849b80)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 56.651s, Critical Path: 0.02s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_sleep_pin_wake has 1 failures.

0.chip_sw_sleep_pin_wake.21876268252168539218169628333605005278344181580760663828171033271277384646048
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_sleep_pin_wake/latest/run.log

  Analyzing: target //sw/device/tests:sleep_pin_wake_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests:sleep_pin_wake_test_sim_dv' failed; build aborted: Target //sw/device/tests:sleep_pin_wake_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests:sleep_pin_wake_test_sim_dv (aa4a55)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 164.307s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_sleep_pin_retention has 1 failures.

0.chip_sw_sleep_pin_retention.108392195939175502263568331929091229811221513401346956641942237740042305475054
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_sleep_pin_retention/latest/run.log

  Analyzing: target //sw/device/tests:sleep_pin_retention_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests:sleep_pin_retention_test_sim_dv' failed; build aborted: Target //sw/device/tests:sleep_pin_retention_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests:sleep_pin_retention_test_sim_dv (9c2035)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 54.641s, Critical Path: 0.02s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

... and 140 more tests.

UVM_FATAL @ * us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat" has 9 failures:
- Test chip_sw_aes_enc_jitter_en has 1 failures.
  - 0.chip_sw_aes_enc_jitter_en.58110864474562536609686886393214855883983490527306562783028868222889007964705
    Line 407, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aes_enc_jitter_en/latest/run.log
```
  UVM_FATAL @  10.340001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_hmac_enc_jitter_en has 1 failures.
  - 0.chip_sw_hmac_enc_jitter_en.95037754679876743592878464607234388718150184446539828334663359809819675161192
    Line 452, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_hmac_enc_jitter_en/latest/run.log
```
  UVM_FATAL @  10.320001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_keymgr_dpe_key_derivation_jitter_en has 1 failures.
  - 0.chip_sw_keymgr_dpe_key_derivation_jitter_en.73736222846138595352127548458039996421633942882438455911428115123775616697317
    Line 458, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation_jitter_en/latest/run.log
```
  UVM_FATAL @  10.180001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.180001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_kmac_mode_kmac_jitter_en has 1 failures.
  - 0.chip_sw_kmac_mode_kmac_jitter_en.9242779274733002550301563405612849985847081197670535406208846732613410462942
    Line 449, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_kmac_mode_kmac_jitter_en/latest/run.log
```
  UVM_FATAL @  10.140001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_aes_enc_jitter_en_reduced_freq has 1 failures.
  - 0.chip_sw_aes_enc_jitter_en_reduced_freq.7568120476395457976656120133937597620796167317899012083519383401854615069962
    Line 424, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aes_enc_jitter_en_reduced_freq/latest/run.log
```
  UVM_FATAL @  10.200001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- ... and 4 more tests.
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode has 3 failures:
- Test chip_csr_bit_bash has 1 failures.
  - 0.chip_csr_bit_bash.17842829404307562900549990518410868919187589434681867622590022875039290264816
    Line 131, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_csr_bit_bash/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_csr_aliasing has 1 failures.
  - 0.chip_csr_aliasing.34272923349652769815259223103259103109519067063206699125970929879984315887451
    Line 131, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_csr_aliasing/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_same_csr_outstanding has 1 failures.
  - 0.chip_same_csr_outstanding.35302881189704699264624403126304100975359758555968571237006820845379988449028
    Line 131, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_same_csr_outstanding/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_base_vseq.sv:434) virtual_sequencer [chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns has 2 failures:
- Test chip_sw_rstmgr_cpu_info has 1 failures.
  - 0.chip_sw_rstmgr_cpu_info.52418675394167255693062808983043671268699434181944346613594101408314032764826
    Line 462, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rstmgr_cpu_info/latest/run.log
```
  UVM_ERROR @ 20025.294899 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 20000000 ns

  UVM_INFO @ 20025.294899 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_aon_timer_irq has 1 failures.
  - 0.chip_sw_aon_timer_irq.56217071282085020353580056010373097431546058206162882382372877642879428312831
    Line 415, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aon_timer_irq/latest/run.log
```
  UVM_ERROR @ 18016.019850 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 18000000 ns

  UVM_INFO @ 18016.019850 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:529) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@46337) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 2 failures:

Test chip_jtag_csr_rw has 1 failures.

0.chip_jtag_csr_rw.19329278381308217237657830705592610747509431071410996037503145011135829107680
Line 6143, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_jtag_csr_rw/latest/run.log

  UVM_ERROR @ 4231.892335 us: (cip_base_scoreboard.sv:529) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@46337) { a_addr: 'h30480000  a_data: 'h813d87e3  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h14  a_opcode: 'h0  a_user: 'h2690e  d_param: 'h0  d_source: 'h14  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 1, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 4231.892335 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_jtag_mem_access has 1 failures.

0.chip_jtag_mem_access.97629117031933927679775172339657363820439510686639814909728994449696355102384
Line 6143, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_jtag_mem_access/latest/run.log

  UVM_ERROR @ 4383.957930 us: (cip_base_scoreboard.sv:529) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@46337) { a_addr: 'h30480000  a_data: 'h46f46b62  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h10  a_opcode: 'h1  a_user: 'h248e1  d_param: 'h0  d_source: 'h10  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 1, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 4383.957930 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (chip_sw_base_vseq.sv:434) virtual_sequencer [chip_sw_rstmgr_cnsty_fault_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns has 1 failures:
- Test chip_sw_rstmgr_rst_cnsty_escalation has 1 failures.
  - 0.chip_sw_rstmgr_rst_cnsty_escalation.57988185055847947139005891702992696138499274916061205857416956448523347181993
    Line 594, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rstmgr_rst_cnsty_escalation/latest/run.log
```
  UVM_ERROR @ 17643.460170 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_rstmgr_cnsty_fault_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 12000000 ns

  UVM_INFO @ 17643.460170 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty has 1 failures:
- Test chip_sw_spi_device_pass_through_collision has 1 failures.
  - 0.chip_sw_spi_device_pass_through_collision.33550790956892765925328818802826382992650880392909205153060943652434885856763
    Line 465, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_spi_device_pass_through_collision/latest/run.log
```
  UVM_ERROR @ 6247.338584 us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty
  UVM_INFO @ 6247.338584 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * us hit, indicating a probable testbench issue has 1 failures:
- Test chip_sw_lc_ctrl_test_locked0_to_scrap has 1 failures.
  - 0.chip_sw_lc_ctrl_test_locked0_to_scrap.99931477804819616249369867278025068845019093061499517217448753973087095288801
    Line 476, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_lc_ctrl_test_locked0_to_scrap/latest/run.log
```
  UVM_FATAL @ 60000.000000 us: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 60000.000000 us hit, indicating a probable testbench issue
  UVM_INFO @ 60000.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_base_vseq.sv:434) virtual_sequencer [chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = * ns has 1 failures:
- Test chip_sw_rstmgr_alert_info has 1 failures.
  - 0.chip_sw_rstmgr_alert_info.79208967318593562960669720099535385324749811653964942122929799568740594751202
    Line 469, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rstmgr_alert_info/latest/run.log
```
  UVM_ERROR @ 30016.770664 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 30000000 ns

  UVM_INFO @ 30016.770664 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_soc_proxy_external_alerts_vseq.sv:74) [chip_sw_soc_proxy_external_alerts_vseq] Check failed alert_rsp == alert_req (* [*] vs * [*]) Alert response incorrect! has 1 failures:
- Test chip_sw_soc_proxy_external_alerts has 1 failures.
  - 0.chip_sw_soc_proxy_external_alerts.8653168686615304631492464107036755487037632979901009888384816644300282725096
    Line 448, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_soc_proxy_external_alerts/latest/run.log
```
  UVM_ERROR @ 4451.258024 us: (chip_sw_soc_proxy_external_alerts_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.chip_sw_soc_proxy_external_alerts_vseq] Check failed alert_rsp == alert_req (93824992236885 [0x555555555555] vs 93824992236886 [0x555555555556]) Alert response incorrect!
  UVM_INFO @ 4451.258024 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [rv_core_ibex_nmi_irq_test_sim_dv(sw/device/tests/rv_core_ibex_nmi_irq_test.c:172)] CHECK-fail: Timed out after * usec (* CPU cycles) waiting for nmi_fired has 1 failures:
- Test chip_sw_rv_core_ibex_nmi_irq has 1 failures.
  - 0.chip_sw_rv_core_ibex_nmi_irq.114432455585906181391508502639157046263453194695395648694807602209951575235913
    Line 421, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rv_core_ibex_nmi_irq/latest/run.log
```
  UVM_ERROR @ 5029.349660 us: (sw_logger_if.sv:526) [rv_core_ibex_nmi_irq_test_sim_dv(sw/device/tests/rv_core_ibex_nmi_irq_test.c:172)] CHECK-fail: Timed out after 1000 usec (100000 CPU cycles) waiting for nmi_fired
  UVM_INFO @ 5029.349660 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:489) [chip_sw_keymgr_dpe_key_derivation_vseq] Check failed keymgr_pkg::KeyWidth'(get_kmac_digest(kmac_key, data_arr)) == act_digest (* [*] vs * [*]) has 1 failures:

Test chip_sw_keymgr_dpe_key_derivation has 1 failures.

0.chip_sw_keymgr_dpe_key_derivation.81248165656262881364438488065151266742316274989435924406763191270298258313822
Line 494, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation/latest/run.log

  UVM_ERROR @ 7624.012280 us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:489) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_dpe_key_derivation_vseq] Check failed keymgr_pkg::KeyWidth'(get_kmac_digest(kmac_key, data_arr)) == act_digest (103927043427049496792382163097690507254259304813219085211893404983799082214813 [0xe5c49f3f0611b08455ed401dd0138f6e280a272463ac8a4643724d622ec9659d] vs 68526058811025324681188574868977366056857307622762261087104647454084972434716 [0x97805ff43e02d9e11bc999b59ec19aca29aadbf0fe420923aece5f8f3528551c])
  UVM_INFO @ 7624.012280 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL @ * us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:74) [chip_sw_keymgr_dpe_key_derivation_vseq] Timed out waiting for keymgr_dpe to derive boot stage * key has 1 failures:
- Test chip_sw_keymgr_dpe_key_derivation_prod has 1 failures.
  - 0.chip_sw_keymgr_dpe_key_derivation_prod.34045502903603603969067185979550195204089837256170164200454439666789277811522
    Line 456, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation_prod/latest/run.log
```
  UVM_FATAL @ 20010.160001 us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_dpe_key_derivation_vseq] Timed out waiting for keymgr_dpe to derive boot stage 0 key
  UVM_INFO @ 20010.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[RamCtn0]] file kmac_app_rom_test_sim_dv.*.vmem could not be opened for r mode has 1 failures:
- Test chip_sw_kmac_app_rom has 1 failures.
  - 0.chip_sw_kmac_app_rom.83075275987805455730238494893701578965543546495371160418738985573460461291264
    Line 457, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_kmac_app_rom/latest/run.log
```
  UVM_FATAL @  10.200001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[RamCtn0]] file kmac_app_rom_test_sim_dv.32.vmem could not be opened for r mode
  UVM_INFO @  10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:529) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_soc_dbg_reg_block, TL item: req: (cip_tl_seq_item@36124) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_tl_errors has 1 failures.

0.chip_tl_errors.71262646620577835483184113074513061226136535050642947282135298332380688109881
Line 254, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_tl_errors/latest/run.log

  UVM_ERROR @ 3702.423560 us: (cip_base_scoreboard.sv:529) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_soc_dbg_reg_block, TL item: req: (cip_tl_seq_item@36124) { a_addr: 'h2213  a_data: 'h54301ee  a_mask: 'h0  a_size: 'h0  a_param: 'h0  a_source: 'hd  a_opcode: 'h4  a_user: 'h25375  d_param: 'h0  d_source: 'hd  d_data: 'h0  d_size: 'h0  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'h4aa  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 1, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 3702.423560 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Error-[CNST-CIF] Constraints inconsistency failure has 1 failures:
- Test chip_padctrl_attributes has 1 failures.
  - 0.chip_padctrl_attributes.42506434944538092769990069285882348909056782444305357774122560103601454726184
    Line 301, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_padctrl_attributes/latest/run.log
```
  Error-[CNST-CIF] Constraints inconsistency failure
  ../src/lowrisc_dv_dv_lib_0/dv_base_test.sv, 95
    Constraints are inconsistent and cannot be solved.
    Please check the inconsistent constraints being printed above and rewrite
    them.
```
UVM_FATAL @ * us: sequencer [sequencer] Item_done() called with no outstanding requests. Each call to item_done() must be paired with a previous call to get_next_item(). has 1 failures:
- Test chip_sw_dma_abort has 1 failures.
  - 0.chip_sw_dma_abort.101985163052958007262429305492024278428773047275890376518386338092038451631774
    Line 426, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_dma_abort/latest/run.log
```
  UVM_FATAL @ 4357.858638 us: uvm_test_top.env.m_spi_device_agents0.sequencer [uvm_test_top.env.m_spi_device_agents0.sequencer] Item_done() called with no outstanding requests. Each call to item_done() must be paired with a previous call to get_next_item().
  UVM_INFO @ 4357.858638 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```