AES/UNMASKED Simulation Results

Thursday April 03 2025 17:08:38 UTC

GitHub Revision: aeb7302

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	5.000s	100.189us	1	1	100.00
V1	smoke	aes_smoke	5.000s	100.027us	1	1	100.00
V1	csr_hw_reset	aes_csr_hw_reset	3.000s	66.914us	1	1	100.00
V1	csr_rw	aes_csr_rw	4.000s	73.587us	1	1	100.00
V1	csr_bit_bash	aes_csr_bit_bash	6.000s	130.850us	1	1	100.00
V1	csr_aliasing	aes_csr_aliasing	5.000s	502.960us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	4.000s	64.469us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	4.000s	73.587us	1	1	100.00
		aes_csr_aliasing	5.000s	502.960us	1	1	100.00
V1		TOTAL			7	7	100.00
V2	algorithm	aes_smoke	5.000s	100.027us	1	1	100.00
		aes_config_error	5.000s	58.443us	1	1	100.00
		aes_stress	6.000s	343.641us	1	1	100.00
V2	key_length	aes_smoke	5.000s	100.027us	1	1	100.00
		aes_config_error	5.000s	58.443us	1	1	100.00
		aes_stress	6.000s	343.641us	1	1	100.00
V2	back2back	aes_stress	6.000s	343.641us	1	1	100.00
		aes_b2b	8.000s	168.015us	1	1	100.00
V2	backpressure	aes_stress	6.000s	343.641us	1	1	100.00
V2	multi_message	aes_smoke	5.000s	100.027us	1	1	100.00
		aes_config_error	5.000s	58.443us	1	1	100.00
		aes_stress	6.000s	343.641us	1	1	100.00
		aes_alert_reset	5.000s	217.450us	1	1	100.00
V2	failure_test	aes_man_cfg_err	5.000s	77.092us	1	1	100.00
		aes_config_error	5.000s	58.443us	1	1	100.00
		aes_alert_reset	5.000s	217.450us	1	1	100.00
V2	trigger_clear_test	aes_clear	6.000s	70.471us	1	1	100.00
V2	nist_test_vectors	aes_nist_vectors	7.000s	170.927us	1	1	100.00
V2	reset_recovery	aes_alert_reset	5.000s	217.450us	1	1	100.00
V2	stress	aes_stress	6.000s	343.641us	1	1	100.00
V2	sideload	aes_stress	6.000s	343.641us	1	1	100.00
		aes_sideload	5.000s	70.683us	1	1	100.00
V2	deinitialization	aes_deinit	5.000s	66.699us	1	1	100.00
V2	stress_all	aes_stress_all	12.000s	845.473us	1	1	100.00
V2	alert_test	aes_alert_test	4.000s	77.920us	1	1	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	4.000s	118.802us	1	1	100.00
V2	tl_d_illegal_access	aes_tl_errors	4.000s	118.802us	1	1	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	3.000s	66.914us	1	1	100.00
		aes_csr_rw	4.000s	73.587us	1	1	100.00
		aes_csr_aliasing	5.000s	502.960us	1	1	100.00
		aes_same_csr_outstanding	4.000s	88.382us	1	1	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	3.000s	66.914us	1	1	100.00
		aes_csr_rw	4.000s	73.587us	1	1	100.00
		aes_csr_aliasing	5.000s	502.960us	1	1	100.00
		aes_same_csr_outstanding	4.000s	88.382us	1	1	100.00
V2		TOTAL			13	13	100.00
V2S	reseeding	aes_reseed	5.000s	154.522us	1	1	100.00
V2S	fault_inject	aes_fi	5.000s	139.317us	1	1	100.00
		aes_control_fi	5.000s	48.060us	1	1	100.00
		aes_cipher_fi	4.000s	50.521us	1	1	100.00
V2S	shadow_reg_update_error	aes_shadow_reg_errors	4.000s	68.143us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	4.000s	68.143us	1	1	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	4.000s	68.143us	1	1	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	4.000s	68.143us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	5.000s	244.514us	1	1	100.00
V2S	tl_intg_err	aes_sec_cm	5.000s	1.994ms	1	1	100.00
		aes_tl_intg_err	5.000s	361.329us	1	1	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	5.000s	361.329us	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	5.000s	217.450us	1	1	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	4.000s	68.143us	1	1	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	5.000s	100.027us	1	1	100.00
		aes_stress	6.000s	343.641us	1	1	100.00
		aes_alert_reset	5.000s	217.450us	1	1	100.00
		aes_core_fi	6.000s	133.055us	1	1	100.00
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	4.000s	68.143us	1	1	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	5.000s	58.590us	1	1	100.00
		aes_stress	6.000s	343.641us	1	1	100.00
V2S	sec_cm_key_sideload	aes_stress	6.000s	343.641us	1	1	100.00
		aes_sideload	5.000s	70.683us	1	1	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	5.000s	58.590us	1	1	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	5.000s	58.590us	1	1	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	5.000s	58.590us	1	1	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	5.000s	58.590us	1	1	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	5.000s	58.590us	1	1	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	6.000s	343.641us	1	1	100.00
V2S	sec_cm_key_masking	aes_stress	6.000s	343.641us	1	1	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	5.000s	139.317us	1	1	100.00
V2S	sec_cm_main_fsm_redun	aes_fi	5.000s	139.317us	1	1	100.00
		aes_control_fi	5.000s	48.060us	1	1	100.00
		aes_cipher_fi	4.000s	50.521us	1	1	100.00
		aes_ctr_fi	4.000s	67.469us	1	1	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	5.000s	139.317us	1	1	100.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	5.000s	139.317us	1	1	100.00
		aes_control_fi	5.000s	48.060us	1	1	100.00
		aes_cipher_fi	4.000s	50.521us	1	1	100.00
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	4.000s	50.521us	1	1	100.00
V2S	sec_cm_ctr_fsm_sparse	aes_fi	5.000s	139.317us	1	1	100.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	5.000s	139.317us	1	1	100.00
		aes_control_fi	5.000s	48.060us	1	1	100.00
		aes_ctr_fi	4.000s	67.469us	1	1	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	5.000s	139.317us	1	1	100.00
		aes_control_fi	5.000s	48.060us	1	1	100.00
		aes_cipher_fi	4.000s	50.521us	1	1	100.00
		aes_ctr_fi	4.000s	67.469us	1	1	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	5.000s	217.450us	1	1	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	5.000s	139.317us	1	1	100.00
		aes_control_fi	5.000s	48.060us	1	1	100.00
		aes_cipher_fi	4.000s	50.521us	1	1	100.00
		aes_ctr_fi	4.000s	67.469us	1	1	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	5.000s	139.317us	1	1	100.00
		aes_control_fi	5.000s	48.060us	1	1	100.00
		aes_cipher_fi	4.000s	50.521us	1	1	100.00
		aes_ctr_fi	4.000s	67.469us	1	1	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	5.000s	139.317us	1	1	100.00
		aes_control_fi	5.000s	48.060us	1	1	100.00
		aes_ctr_fi	4.000s	67.469us	1	1	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	5.000s	139.317us	1	1	100.00
		aes_control_fi	5.000s	48.060us	1	1	100.00
		aes_cipher_fi	4.000s	50.521us	1	1	100.00
V2S		TOTAL			11	11	100.00
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	4.000s	49.695us	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			31	32	96.88

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:587) [aes_alert_reset_vseq] Check failed * == local_alert_agent_cfg.vif.get_alert() (* [*] vs * [*]) Alert recov_ctrl_update_err fired unexpectedly! has 1 failures:
  • Test aes_stress_all_with_rand_reset has 1 failures.

    • 0.aes_stress_all_with_rand_reset.74792517276772283622291094189381003027879325973314838208150733962924403579499
      Line 127, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @  49695449 ps: (cip_base_vseq.sv:587) [uvm_test_top.env.virtual_sequencer.aes_alert_reset_vseq] Check failed 0 == local_alert_agent_cfg.vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert recov_ctrl_update_err fired unexpectedly!
        UVM_INFO @  49695449 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---