DMA Simulation Results

Thursday April 03 2025 17:08:38 UTC

GitHub Revision: aeb7302

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	dma_memory_smoke	dma_memory_smoke	8.000s	1.196ms	1	1	100.00
V1	dma_handshake_smoke	dma_handshake_smoke	6.000s	854.041us	1	1	100.00
V1	dma_generic_smoke	dma_generic_smoke	8.000s	402.432us	1	1	100.00
V1	csr_hw_reset	dma_csr_hw_reset	4.000s	37.818us	1	1	100.00
V1	csr_rw	dma_csr_rw	4.000s	87.091us	1	1	100.00
V1	csr_bit_bash	dma_csr_bit_bash	11.000s	298.454us	1	1	100.00
V1	csr_aliasing	dma_csr_aliasing	6.000s	305.828us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	dma_csr_mem_rw_with_rand_reset	4.000s	47.518us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	dma_csr_rw	4.000s	87.091us	1	1	100.00
		dma_csr_aliasing	6.000s	305.828us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	dma_memory_region_lock	dma_memory_region_lock	27.000s	2.107ms	1	1	100.00
V2	dma_handshake_stress	dma_handshake_stress	5.850m	670.285ms	1	1	100.00
V2	dma_memory_stress	dma_memory_stress	1.000m	3.938ms	1	1	100.00
V2	dma_generic_stress	dma_generic_stress	2.267m	74.765ms	1	1	100.00
V2	dma_handshake_mem_buffer_overflow	dma_handshake_stress	5.850m	670.285ms	1	1	100.00
V2	dma_abort	dma_abort	10.000s	492.015us	1	1	100.00
V2	dma_stress_all	dma_stress_all	2.683m	14.162ms	1	1	100.00
V2	intr_test	dma_intr_test	4.000s	13.827us	1	1	100.00
V2	tl_d_oob_addr_access	dma_tl_errors	6.000s	484.460us	1	1	100.00
V2	tl_d_illegal_access	dma_tl_errors	6.000s	484.460us	1	1	100.00
V2	tl_d_outstanding_access	dma_csr_hw_reset	4.000s	37.818us	1	1	100.00
		dma_csr_rw	4.000s	87.091us	1	1	100.00
		dma_csr_aliasing	6.000s	305.828us	1	1	100.00
		dma_same_csr_outstanding	5.000s	271.058us	1	1	100.00
V2	tl_d_partial_access	dma_csr_hw_reset	4.000s	37.818us	1	1	100.00
		dma_csr_rw	4.000s	87.091us	1	1	100.00
		dma_csr_aliasing	6.000s	305.828us	1	1	100.00
		dma_same_csr_outstanding	5.000s	271.058us	1	1	100.00
V2		TOTAL			9	9	100.00
V2S	dma_illegal_addr_range	dma_mem_enabled	17.000s	253.625us	1	1	100.00
		dma_generic_stress	2.267m	74.765ms	1	1	100.00
		dma_handshake_stress	5.850m	670.285ms	1	1	100.00
V2S	tl_intg_err	dma_tl_intg_err	6.000s	213.850us	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	dma_short_transfer	53.000s	14.330ms	1	1	100.00
		dma_longer_transfer	27.000s	1.619ms	1	1	100.00
		TOTAL			21	21	100.00