EDN Simulation Results

Thursday April 03 2025 17:08:38 UTC

GitHub Revision: aeb7302

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke edn_smoke 1.770s 34.101us 1 1 100.00
V1 csr_hw_reset edn_csr_hw_reset 1.940s 37.085us 1 1 100.00
V1 csr_rw edn_csr_rw 1.540s 132.869us 1 1 100.00
V1 csr_bit_bash edn_csr_bit_bash 2.990s 117.687us 1 1 100.00
V1 csr_aliasing edn_csr_aliasing 1.810s 36.512us 1 1 100.00
V1 csr_mem_rw_with_rand_reset edn_csr_mem_rw_with_rand_reset 2.190s 52.307us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr edn_csr_rw 1.540s 132.869us 1 1 100.00
edn_csr_aliasing 1.810s 36.512us 1 1 100.00
V1 TOTAL 6 6 100.00
V2 firmware edn_genbits 1.960s 34.335us 1 1 100.00
V2 csrng_commands edn_genbits 1.960s 34.335us 1 1 100.00
V2 genbits edn_genbits 1.960s 34.335us 1 1 100.00
V2 interrupts edn_intr 1.780s 76.905us 1 1 100.00
V2 alerts edn_alert 2.210s 107.685us 1 1 100.00
V2 errs edn_err 2.000s 20.463us 1 1 100.00
V2 disable edn_disable 1.730s 18.356us 1 1 100.00
edn_disable_auto_req_mode 1.790s 74.726us 1 1 100.00
V2 stress_all edn_stress_all 3.750s 347.661us 1 1 100.00
V2 intr_test edn_intr_test 1.570s 69.147us 1 1 100.00
V2 alert_test edn_alert_test 1.920s 44.064us 1 1 100.00
V2 tl_d_oob_addr_access edn_tl_errors 2.840s 25.205us 1 1 100.00
V2 tl_d_illegal_access edn_tl_errors 2.840s 25.205us 1 1 100.00
V2 tl_d_outstanding_access edn_csr_hw_reset 1.940s 37.085us 1 1 100.00
edn_csr_rw 1.540s 132.869us 1 1 100.00
edn_csr_aliasing 1.810s 36.512us 1 1 100.00
edn_same_csr_outstanding 2.400s 29.262us 1 1 100.00
V2 tl_d_partial_access edn_csr_hw_reset 1.940s 37.085us 1 1 100.00
edn_csr_rw 1.540s 132.869us 1 1 100.00
edn_csr_aliasing 1.810s 36.512us 1 1 100.00
edn_same_csr_outstanding 2.400s 29.262us 1 1 100.00
V2 TOTAL 11 11 100.00
V2S tl_intg_err edn_sec_cm 7.070s 1.043ms 1 1 100.00
edn_tl_intg_err 3.270s 157.429us 1 1 100.00
V2S sec_cm_config_regwen edn_regwen 1.640s 21.202us 1 1 100.00
V2S sec_cm_config_mubi edn_alert 2.210s 107.685us 1 1 100.00
V2S sec_cm_main_sm_fsm_sparse edn_sec_cm 7.070s 1.043ms 1 1 100.00
V2S sec_cm_ack_sm_fsm_sparse edn_sec_cm 7.070s 1.043ms 1 1 100.00
V2S sec_cm_fifo_ctr_redun edn_sec_cm 7.070s 1.043ms 1 1 100.00
V2S sec_cm_ctr_redun edn_sec_cm 7.070s 1.043ms 1 1 100.00
V2S sec_cm_main_sm_ctr_local_esc edn_alert 2.210s 107.685us 1 1 100.00
edn_sec_cm 7.070s 1.043ms 1 1 100.00
V2S sec_cm_cs_rdata_bus_consistency edn_alert 2.210s 107.685us 1 1 100.00
V2S sec_cm_tile_link_bus_integrity edn_tl_intg_err 3.270s 157.429us 1 1 100.00
V2S TOTAL 3 3 100.00
V3 stress_all_with_rand_reset edn_stress_all_with_rand_reset 0 1 0.00
V3 TOTAL 0 1 0.00
TOTAL 20 21 95.24

Failure Buckets