HMAC Simulation Results

Thursday April 03 2025 17:08:38 UTC

GitHub Revision: aeb7302

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke hmac_smoke 11.130s 5.345ms 1 1 100.00
V1 csr_hw_reset hmac_csr_hw_reset 1.560s 108.832us 1 1 100.00
V1 csr_rw hmac_csr_rw 1.760s 133.641us 1 1 100.00
V1 csr_bit_bash hmac_csr_bit_bash 7.900s 722.255us 1 1 100.00
V1 csr_aliasing hmac_csr_aliasing 3.240s 2.165ms 1 1 100.00
V1 csr_mem_rw_with_rand_reset hmac_csr_mem_rw_with_rand_reset 2.520s 73.679us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr hmac_csr_rw 1.760s 133.641us 1 1 100.00
hmac_csr_aliasing 3.240s 2.165ms 1 1 100.00
V1 TOTAL 6 6 100.00
V2 long_msg hmac_long_msg 33.060s 16.773ms 1 1 100.00
V2 back_pressure hmac_back_pressure 21.680s 494.213us 1 1 100.00
V2 test_vectors hmac_test_sha256_vectors 8.490s 304.914us 1 1 100.00
hmac_test_sha384_vectors 6.934m 59.812ms 1 1 100.00
hmac_test_sha512_vectors 6.245m 25.973ms 1 1 100.00
hmac_test_hmac256_vectors 6.550s 388.761us 1 1 100.00
hmac_test_hmac384_vectors 8.680s 3.153ms 1 1 100.00
hmac_test_hmac512_vectors 13.300s 407.596us 1 1 100.00
V2 burst_wr hmac_burst_wr 9.400s 489.719us 1 1 100.00
V2 datapath_stress hmac_datapath_stress 9.779m 4.716ms 1 1 100.00
V2 error hmac_error 57.650s 6.577ms 1 1 100.00
V2 wipe_secret hmac_wipe_secret 13.100s 1.431ms 1 1 100.00
V2 save_and_restore hmac_smoke 11.130s 5.345ms 1 1 100.00
hmac_long_msg 33.060s 16.773ms 1 1 100.00
hmac_back_pressure 21.680s 494.213us 1 1 100.00
hmac_datapath_stress 9.779m 4.716ms 1 1 100.00
hmac_burst_wr 9.400s 489.719us 1 1 100.00
hmac_stress_all 1.508m 28.656ms 1 1 100.00
V2 fifo_empty_status_interrupt hmac_smoke 11.130s 5.345ms 1 1 100.00
hmac_long_msg 33.060s 16.773ms 1 1 100.00
hmac_back_pressure 21.680s 494.213us 1 1 100.00
hmac_datapath_stress 9.779m 4.716ms 1 1 100.00
hmac_wipe_secret 13.100s 1.431ms 1 1 100.00
hmac_test_sha256_vectors 8.490s 304.914us 1 1 100.00
hmac_test_sha384_vectors 6.934m 59.812ms 1 1 100.00
hmac_test_sha512_vectors 6.245m 25.973ms 1 1 100.00
hmac_test_hmac256_vectors 6.550s 388.761us 1 1 100.00
hmac_test_hmac384_vectors 8.680s 3.153ms 1 1 100.00
hmac_test_hmac512_vectors 13.300s 407.596us 1 1 100.00
V2 wide_digest_configurable_key_length hmac_smoke 11.130s 5.345ms 1 1 100.00
hmac_long_msg 33.060s 16.773ms 1 1 100.00
hmac_back_pressure 21.680s 494.213us 1 1 100.00
hmac_datapath_stress 9.779m 4.716ms 1 1 100.00
hmac_burst_wr 9.400s 489.719us 1 1 100.00
hmac_error 57.650s 6.577ms 1 1 100.00
hmac_wipe_secret 13.100s 1.431ms 1 1 100.00
hmac_test_sha256_vectors 8.490s 304.914us 1 1 100.00
hmac_test_sha384_vectors 6.934m 59.812ms 1 1 100.00
hmac_test_sha512_vectors 6.245m 25.973ms 1 1 100.00
hmac_test_hmac256_vectors 6.550s 388.761us 1 1 100.00
hmac_test_hmac384_vectors 8.680s 3.153ms 1 1 100.00
hmac_test_hmac512_vectors 13.300s 407.596us 1 1 100.00
hmac_stress_all 1.508m 28.656ms 1 1 100.00
V2 stress_all hmac_stress_all 1.508m 28.656ms 1 1 100.00
V2 alert_test hmac_alert_test 1.430s 28.963us 1 1 100.00
V2 intr_test hmac_intr_test 1.450s 164.204us 1 1 100.00
V2 tl_d_oob_addr_access hmac_tl_errors 2.790s 178.113us 1 1 100.00
V2 tl_d_illegal_access hmac_tl_errors 2.790s 178.113us 1 1 100.00
V2 tl_d_outstanding_access hmac_csr_hw_reset 1.560s 108.832us 1 1 100.00
hmac_csr_rw 1.760s 133.641us 1 1 100.00
hmac_csr_aliasing 3.240s 2.165ms 1 1 100.00
hmac_same_csr_outstanding 2.550s 829.399us 1 1 100.00
V2 tl_d_partial_access hmac_csr_hw_reset 1.560s 108.832us 1 1 100.00
hmac_csr_rw 1.760s 133.641us 1 1 100.00
hmac_csr_aliasing 3.240s 2.165ms 1 1 100.00
hmac_same_csr_outstanding 2.550s 829.399us 1 1 100.00
V2 TOTAL 17 17 100.00
V2S tl_intg_err hmac_sec_cm 1.720s 121.012us 1 1 100.00
hmac_tl_intg_err 2.300s 179.868us 1 1 100.00
V2S sec_cm_bus_integrity hmac_tl_intg_err 2.300s 179.868us 1 1 100.00
V2S TOTAL 2 2 100.00
V3 write_config_and_secret_key_during_msg_wr hmac_smoke 11.130s 5.345ms 1 1 100.00
V3 stress_reset hmac_stress_reset 1.970s 92.104us 1 1 100.00
V3 stress_all_with_rand_reset hmac_stress_all_with_rand_reset 1.910m 79.894ms 1 1 100.00
V3 TOTAL 2 2 100.00
Unmapped tests hmac_directed 1.820s 80.912us 1 1 100.00
TOTAL 28 28 100.00