I2C Simulation Results

Thursday April 03 2025 17:08:38 UTC

GitHub Revision: `aeb7302`

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	host_smoke	i2c_host_smoke	42.050s	2.761ms	1	1	100.00
V1	target_smoke	i2c_target_smoke	9.610s	1.026ms	1	1	100.00
V1	csr_hw_reset	i2c_csr_hw_reset	1.680s	58.066us	1	1	100.00
V1	csr_rw	i2c_csr_rw	1.740s	293.629us	1	1	100.00
V1	csr_bit_bash	i2c_csr_bit_bash	3.230s	588.437us	1	1	100.00
V1	csr_aliasing	i2c_csr_aliasing	1.950s	55.793us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	i2c_csr_mem_rw_with_rand_reset	1.900s	40.909us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	i2c_csr_rw	1.740s	293.629us	1	1	100.00
		i2c_csr_aliasing	1.950s	55.793us	1	1	100.00
V1		TOTAL			7	7	100.00
V2	host_error_intr	i2c_host_error_intr	2.510s	136.042us	1	1	100.00
V2	host_stress_all	i2c_host_stress_all	10.778m	10.637ms	0	1	0.00
V2	host_maxperf	i2c_host_perf	2.875m	12.665ms	1	1	100.00
V2	host_override	i2c_host_override	1.870s	177.701us	1	1	100.00
V2	host_fifo_watermark	i2c_host_fifo_watermark	3.394m	18.608ms	1	1	100.00
V2	host_fifo_overflow	i2c_host_fifo_overflow	53.560s	10.235ms	1	1	100.00
V2	host_fifo_reset	i2c_host_fifo_reset_fmt	1.910s	574.537us	1	1	100.00
		i2c_host_fifo_fmt_empty	6.280s	1.605ms	1	1	100.00
		i2c_host_fifo_reset_rx	3.830s	215.947us	1	1	100.00
V2	host_fifo_full	i2c_host_fifo_full	1.727m	9.756ms	1	1	100.00
V2	host_timeout	i2c_host_stretch_timeout	14.730s	2.026ms	1	1	100.00
V2	i2c_host_mode_toggle	i2c_host_mode_toggle	2.280s	390.590us	1	1	100.00
V2	target_glitch	i2c_target_glitch	6.300s	6.520ms	1	1	100.00
V2	target_stress_all	i2c_target_stress_all	23.980s	28.236ms	1	1	100.00
V2	target_maxperf	i2c_target_perf	4.130s	707.685us	1	1	100.00
V2	target_fifo_empty	i2c_target_stress_rd	26.530s	3.247ms	1	1	100.00
		i2c_target_intr_smoke	6.310s	3.501ms	1	1	100.00
V2	target_fifo_reset	i2c_target_fifo_reset_acq	1.750s	173.435us	1	1	100.00
		i2c_target_fifo_reset_tx	1.740s	438.187us	1	1	100.00
V2	target_fifo_full	i2c_target_stress_wr	2.228m	43.723ms	1	1	100.00
		i2c_target_stress_rd	26.530s	3.247ms	1	1	100.00
		i2c_target_intr_stress_wr	1.236m	19.259ms	1	1	100.00
V2	target_timeout	i2c_target_timeout	5.480s	5.837ms	1	1	100.00
V2	target_clock_stretch	i2c_target_stretch	36.950s	5.299ms	1	1	100.00
V2	bad_address	i2c_target_bad_addr	4.360s	1.016ms	1	1	100.00
V2	target_mode_glitch	i2c_target_hrst	2.340s	254.362us	1	1	100.00
V2	target_fifo_watermark	i2c_target_fifo_watermarks_acq	2.710s	1.957ms	1	1	100.00
		i2c_target_fifo_watermarks_tx	1.830s	135.285us	1	1	100.00
V2	host_mode_config_perf	i2c_host_perf	2.875m	12.665ms	1	1	100.00
		i2c_host_perf_precise	5.170s	696.919us	1	1	100.00
V2	host_mode_clock_stretching	i2c_host_stretch_timeout	14.730s	2.026ms	1	1	100.00
V2	target_mode_tx_stretch_ctrl	i2c_target_tx_stretch_ctrl	1.990s	43.360us	1	1	100.00
V2	target_mode_nack_generation	i2c_target_nack_acqfull	3.200s	1.645ms	1	1	100.00
		i2c_target_nack_acqfull_addr	3.510s	565.731us	1	1	100.00
		i2c_target_nack_txstretch	1.780s	128.267us	0	1	0.00
V2	host_mode_halt_on_nak	i2c_host_may_nack	16.560s	3.343ms	1	1	100.00
V2	target_mode_smbus_maxlen	i2c_target_smbus_maxlen	2.540s	769.281us	1	1	100.00
V2	alert_test	i2c_alert_test	1.540s	17.125us	1	1	100.00
V2	intr_test	i2c_intr_test	1.700s	18.572us	1	1	100.00
V2	tl_d_oob_addr_access	i2c_tl_errors	2.300s	52.078us	1	1	100.00
V2	tl_d_illegal_access	i2c_tl_errors	2.300s	52.078us	1	1	100.00
V2	tl_d_outstanding_access	i2c_csr_hw_reset	1.680s	58.066us	1	1	100.00
		i2c_csr_rw	1.740s	293.629us	1	1	100.00
		i2c_csr_aliasing	1.950s	55.793us	1	1	100.00
		i2c_same_csr_outstanding	1.770s	34.160us	1	1	100.00
V2	tl_d_partial_access	i2c_csr_hw_reset	1.680s	58.066us	1	1	100.00
		i2c_csr_rw	1.740s	293.629us	1	1	100.00
		i2c_csr_aliasing	1.950s	55.793us	1	1	100.00
		i2c_same_csr_outstanding	1.770s	34.160us	1	1	100.00
V2		TOTAL			36	38	94.74
V2S	tl_intg_err	i2c_tl_intg_err	2.220s	284.745us	1	1	100.00
		i2c_sec_cm	1.610s	679.136us	1	1	100.00
V2S	sec_cm_bus_integrity	i2c_tl_intg_err	2.220s	284.745us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	host_stress_all_with_rand_reset	i2c_host_stress_all_with_rand_reset	3.650s	475.353us	0	1	0.00
V3	target_error_intr	i2c_target_unexp_stop	2.090s	1.457ms	0	1	0.00
V3	target_stress_all_with_rand_reset	i2c_target_stress_all_with_rand_reset	7.170s	1.814ms	0	1	0.00
V3		TOTAL			0	3	0.00
		TOTAL			45	50	90.00

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:907) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 2 failures:
- Test i2c_host_stress_all_with_rand_reset has 1 failures.
  - 0.i2c_host_stress_all_with_rand_reset.32147887755012867400033053791114949664886784309999189354939909576304211113362
    Line 87, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 475352867 ps: (cip_base_vseq.sv:907) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 475352867 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test i2c_target_stress_all_with_rand_reset has 1 failures.
  - 0.i2c_target_stress_all_with_rand_reset.85979373507304355348329608683362149392655423425440283106015956343766917832333
    Line 90, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1814408545 ps: (cip_base_vseq.sv:907) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1814408545 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (i2c_scoreboard.sv:717) [scoreboard] controller_mode_wr_obs_fifo item uncompared: has 1 failures:

Test i2c_host_stress_all has 1 failures.

0.i2c_host_stress_all.43475729141897663291501291840426080415978648633506974250151450967047520395221
Line 116, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all/latest/run.log

  UVM_ERROR @ 10637160347 ps: (i2c_scoreboard.sv:717) [uvm_test_top.env.scoreboard] controller_mode_wr_obs_fifo item uncompared:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------
  mon_dut_item    i2c_item            -     @11056272

UVM_ERROR (i2c_base_vseq.sv:1474) [i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (* [*] vs * [*]) has 1 failures:
- Test i2c_target_unexp_stop has 1 failures.
  - 0.i2c_target_unexp_stop.80047029417734580018431491980674311261913415561730029730663174950387606338576
    Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log
```
  UVM_ERROR @ 1457104503 ps: (i2c_base_vseq.sv:1474) [uvm_test_top.env.virtual_sequencer.i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 1457104503 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: i2c_reg_block.target_nack_count reset value: * has 1 failures:
- Test i2c_target_nack_txstretch has 1 failures.
  - 0.i2c_target_nack_txstretch.10460955328675514113277881944820555209599566343288388678125874463201202482862
    Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_nack_txstretch/latest/run.log
```
  UVM_ERROR @ 128267307 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.target_nack_count reset value: 0x0
  UVM_INFO @ 128267307 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```