KEYMGR Simulation Results

Thursday April 03 2025 17:08:38 UTC

GitHub Revision: aeb7302

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	keymgr_smoke	8.510s	460.531us	1	1	100.00
V1	random	keymgr_random	3.100s	172.582us	1	1	100.00
V1	csr_hw_reset	keymgr_csr_hw_reset	2.160s	147.986us	1	1	100.00
V1	csr_rw	keymgr_csr_rw	2.180s	85.273us	1	1	100.00
V1	csr_bit_bash	keymgr_csr_bit_bash	18.010s	2.374ms	1	1	100.00
V1	csr_aliasing	keymgr_csr_aliasing	4.320s	741.513us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	keymgr_csr_mem_rw_with_rand_reset	1.910s	48.685us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	keymgr_csr_rw	2.180s	85.273us	1	1	100.00
		keymgr_csr_aliasing	4.320s	741.513us	1	1	100.00
V1		TOTAL			7	7	100.00
V2	cfgen_during_op	keymgr_cfg_regwen	3.290s	168.260us	1	1	100.00
V2	sideload	keymgr_sideload	4.030s	97.329us	1	1	100.00
		keymgr_sideload_kmac	6.330s	299.758us	1	1	100.00
		keymgr_sideload_aes	5.600s	666.137us	1	1	100.00
		keymgr_sideload_otbn	2.940s	51.049us	1	1	100.00
V2	direct_to_disabled_state	keymgr_direct_to_disabled	6.760s	1.468ms	1	1	100.00
V2	lc_disable	keymgr_lc_disable	3.320s	283.148us	1	1	100.00
V2	kmac_error_response	keymgr_kmac_rsp_err	3.250s	196.861us	1	1	100.00
V2	invalid_sw_input	keymgr_sw_invalid_input	5.410s	235.384us	1	1	100.00
V2	invalid_hw_input	keymgr_hwsw_invalid_input	3.100s	109.083us	1	1	100.00
V2	sync_async_fault_cross	keymgr_sync_async_fault_cross	3.840s	100.558us	1	1	100.00
V2	stress_all	keymgr_stress_all	4.031m	99.425ms	1	1	100.00
V2	intr_test	keymgr_intr_test	1.770s	36.004us	1	1	100.00
V2	alert_test	keymgr_alert_test	1.630s	19.597us	1	1	100.00
V2	tl_d_oob_addr_access	keymgr_tl_errors	1.860s	93.416us	1	1	100.00
V2	tl_d_illegal_access	keymgr_tl_errors	1.860s	93.416us	1	1	100.00
V2	tl_d_outstanding_access	keymgr_csr_hw_reset	2.160s	147.986us	1	1	100.00
		keymgr_csr_rw	2.180s	85.273us	1	1	100.00
		keymgr_csr_aliasing	4.320s	741.513us	1	1	100.00
		keymgr_same_csr_outstanding	3.000s	93.506us	1	1	100.00
V2	tl_d_partial_access	keymgr_csr_hw_reset	2.160s	147.986us	1	1	100.00
		keymgr_csr_rw	2.180s	85.273us	1	1	100.00
		keymgr_csr_aliasing	4.320s	741.513us	1	1	100.00
		keymgr_same_csr_outstanding	3.000s	93.506us	1	1	100.00
V2		TOTAL			16	16	100.00
V2S	sec_cm_additional_check	keymgr_sec_cm	6.450s	349.629us	1	1	100.00
V2S	tl_intg_err	keymgr_sec_cm	6.450s	349.629us	1	1	100.00
		keymgr_tl_intg_err	7.150s	908.992us	1	1	100.00
V2S	shadow_reg_update_error	keymgr_shadow_reg_errors	2.870s	612.712us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	keymgr_shadow_reg_errors	2.870s	612.712us	1	1	100.00
V2S	shadow_reg_storage_error	keymgr_shadow_reg_errors	2.870s	612.712us	1	1	100.00
V2S	shadowed_reset_glitch	keymgr_shadow_reg_errors	2.870s	612.712us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	keymgr_shadow_reg_errors_with_csr_rw	1.840s	44.520us	0	1	0.00
V2S	prim_count_check	keymgr_sec_cm	6.450s	349.629us	1	1	100.00
V2S	prim_fsm_check	keymgr_sec_cm	6.450s	349.629us	1	1	100.00
V2S	sec_cm_bus_integrity	keymgr_tl_intg_err	7.150s	908.992us	1	1	100.00
V2S	sec_cm_config_shadow	keymgr_shadow_reg_errors	2.870s	612.712us	1	1	100.00
V2S	sec_cm_op_config_regwen	keymgr_cfg_regwen	3.290s	168.260us	1	1	100.00
V2S	sec_cm_reseed_config_regwen	keymgr_random	3.100s	172.582us	1	1	100.00
		keymgr_csr_rw	2.180s	85.273us	1	1	100.00
V2S	sec_cm_sw_binding_config_regwen	keymgr_random	3.100s	172.582us	1	1	100.00
		keymgr_csr_rw	2.180s	85.273us	1	1	100.00
V2S	sec_cm_max_key_ver_config_regwen	keymgr_random	3.100s	172.582us	1	1	100.00
		keymgr_csr_rw	2.180s	85.273us	1	1	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	keymgr_lc_disable	3.320s	283.148us	1	1	100.00
V2S	sec_cm_constants_consistency	keymgr_hwsw_invalid_input	3.100s	109.083us	1	1	100.00
V2S	sec_cm_intersig_consistency	keymgr_hwsw_invalid_input	3.100s	109.083us	1	1	100.00
V2S	sec_cm_hw_key_sw_noaccess	keymgr_random	3.100s	172.582us	1	1	100.00
V2S	sec_cm_output_keys_ctrl_redun	keymgr_sideload_protect	3.480s	205.708us	1	1	100.00
V2S	sec_cm_ctrl_fsm_sparse	keymgr_sec_cm	6.450s	349.629us	1	1	100.00
V2S	sec_cm_data_fsm_sparse	keymgr_sec_cm	6.450s	349.629us	1	1	100.00
V2S	sec_cm_ctrl_fsm_local_esc	keymgr_sec_cm	6.450s	349.629us	1	1	100.00
V2S	sec_cm_ctrl_fsm_consistency	keymgr_custom_cm	3.380s	84.897us	1	1	100.00
V2S	sec_cm_ctrl_fsm_global_esc	keymgr_lc_disable	3.320s	283.148us	1	1	100.00
V2S	sec_cm_ctrl_ctr_redun	keymgr_sec_cm	6.450s	349.629us	1	1	100.00
V2S	sec_cm_kmac_if_fsm_sparse	keymgr_sec_cm	6.450s	349.629us	1	1	100.00
V2S	sec_cm_kmac_if_ctr_redun	keymgr_sec_cm	6.450s	349.629us	1	1	100.00
V2S	sec_cm_kmac_if_cmd_ctrl_consistency	keymgr_custom_cm	3.380s	84.897us	1	1	100.00
V2S	sec_cm_kmac_if_done_ctrl_consistency	keymgr_custom_cm	3.380s	84.897us	1	1	100.00
V2S	sec_cm_reseed_ctr_redun	keymgr_sec_cm	6.450s	349.629us	1	1	100.00
V2S	sec_cm_side_load_sel_ctrl_consistency	keymgr_custom_cm	3.380s	84.897us	1	1	100.00
V2S	sec_cm_sideload_ctrl_fsm_sparse	keymgr_sec_cm	6.450s	349.629us	1	1	100.00
V2S	sec_cm_ctrl_key_integrity	keymgr_custom_cm	3.380s	84.897us	1	1	100.00
V2S		TOTAL			5	6	83.33
V3	stress_all_with_rand_reset	keymgr_stress_all_with_rand_reset	7.160s	238.881us	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			29	30	96.67

Failure Buckets

• Offending '(d2h.d_error || ((d2h.d_data & *) == (exp_vals[*] & *)))' has 1 failures:
  • Test keymgr_shadow_reg_errors_with_csr_rw has 1 failures.

    • 0.keymgr_shadow_reg_errors_with_csr_rw.14701134170392554744995934715789480860321015281196551403185070689966854490976
      Line 79, in log /nightly/runs/scratch/master/keymgr-sim-vcs/0.keymgr_shadow_reg_errors_with_csr_rw/latest/run.log

            Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[10] & 'hffffffff)))'
        UVM_ERROR @  44519601 ps: (keymgr_csr_assert_fpv.sv:416) [ASSERT FAILED] sealing_sw_binding_5_rd_A
        UVM_INFO @  44519601 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---