KMAC/UNMASKED Simulation Results

Thursday April 03 2025 17:08:38 UTC

GitHub Revision: aeb7302

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	14.720s	5.898ms	1	1	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	2.020s	108.842us	1	1	100.00
V1	csr_rw	kmac_csr_rw	1.780s	26.826us	1	1	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	13.690s	1.528ms	1	1	100.00
V1	csr_aliasing	kmac_csr_aliasing	4.650s	1.315ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.360s	78.074us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.780s	26.826us	1	1	100.00
		kmac_csr_aliasing	4.650s	1.315ms	1	1	100.00
V1	mem_walk	kmac_mem_walk	1.740s	18.038us	1	1	100.00
V1	mem_partial_access	kmac_mem_partial_access	2.170s	20.640us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	11.014m	37.827ms	1	1	100.00
V2	burst_write	kmac_burst_write	7.070m	15.931ms	1	1	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	23.600s	644.079us	1	1	100.00
		kmac_test_vectors_sha3_256	24.980m	186.058ms	1	1	100.00
		kmac_test_vectors_sha3_384	19.310s	4.579ms	1	1	100.00
		kmac_test_vectors_sha3_512	9.370m	31.608ms	1	1	100.00
		kmac_test_vectors_shake_128	2.059m	50.973ms	1	1	100.00
		kmac_test_vectors_shake_256	1.127m	2.796ms	1	1	100.00
		kmac_test_vectors_kmac	2.490s	109.105us	1	1	100.00
		kmac_test_vectors_kmac_xof	2.770s	120.683us	1	1	100.00
V2	sideload	kmac_sideload	22.510s	3.044ms	1	1	100.00
V2	app	kmac_app	1.276m	2.382ms	1	1	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	2.944m	33.710ms	1	1	100.00
V2	entropy_refresh	kmac_entropy_refresh	9.750s	2.891ms	1	1	100.00
V2	error	kmac_error	1.928m	6.434ms	1	1	100.00
V2	key_error	kmac_key_error	2.400s	154.027us	1	1	100.00
V2	sideload_invalid	kmac_sideload_invalid	41.140s	10.089ms	0	1	0.00
V2	edn_timeout_error	kmac_edn_timeout_error	9.180s	408.461us	1	1	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	18.480s	1.011ms	1	1	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	22.540s	9.050ms	1	1	100.00
V2	lc_escalation	kmac_lc_escalation	2.390s	56.859us	1	1	100.00
V2	stress_all	kmac_stress_all	1.211m	2.417ms	1	1	100.00
V2	intr_test	kmac_intr_test	1.860s	38.988us	1	1	100.00
V2	alert_test	kmac_alert_test	1.900s	44.945us	1	1	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	2.680s	120.871us	1	1	100.00
V2	tl_d_illegal_access	kmac_tl_errors	2.680s	120.871us	1	1	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	2.020s	108.842us	1	1	100.00
		kmac_csr_rw	1.780s	26.826us	1	1	100.00
		kmac_csr_aliasing	4.650s	1.315ms	1	1	100.00
		kmac_same_csr_outstanding	2.710s	303.326us	1	1	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	2.020s	108.842us	1	1	100.00
		kmac_csr_rw	1.780s	26.826us	1	1	100.00
		kmac_csr_aliasing	4.650s	1.315ms	1	1	100.00
		kmac_same_csr_outstanding	2.710s	303.326us	1	1	100.00
V2		TOTAL			25	26	96.15
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	2.230s	70.295us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	2.230s	70.295us	1	1	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	2.230s	70.295us	1	1	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	2.230s	70.295us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	4.000s	2.280ms	1	1	100.00
V2S	tl_intg_err	kmac_sec_cm	19.950s	2.227ms	1	1	100.00
		kmac_tl_intg_err	3.860s	416.617us	1	1	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	3.860s	416.617us	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	2.390s	56.859us	1	1	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	14.720s	5.898ms	1	1	100.00
V2S	sec_cm_key_sideload	kmac_sideload	22.510s	3.044ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	2.230s	70.295us	1	1	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	19.950s	2.227ms	1	1	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	19.950s	2.227ms	1	1	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	19.950s	2.227ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	14.720s	5.898ms	1	1	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	2.390s	56.859us	1	1	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	19.950s	2.227ms	1	1	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	1.933m	59.364ms	1	1	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	14.720s	5.898ms	1	1	100.00
V2S		TOTAL			5	5	100.00
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	3.810s	337.200us	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			38	40	95.00

Failure Buckets

• UVM_FATAL (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=7) has 1 failures:

  • Test kmac_sideload_invalid has 1 failures.

    • 0.kmac_sideload_invalid.19616972136253332691462735745622852156749791918144908439299804888778795166025
      Line 80, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/0.kmac_sideload_invalid/latest/run.log

        UVM_FATAL @ 10088687755 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=0xb9b1a000, Comparison=CompareOpEq, exp_data=0x1, call_count=7)
        UVM_INFO @ 10088687755 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (kmac_scoreboard.sv:1202) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 1 failures:

  • Test kmac_stress_all_with_rand_reset has 1 failures.

    • 0.kmac_stress_all_with_rand_reset.37313899510897682202731433294711241418488676443476653525301696656028219412119
      Line 80, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 337200277 ps: (kmac_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483728 [0x80000050]) reg name: kmac_reg_block.err_code
        UVM_INFO @ 337200277 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---