aeb7302| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | mbx_smoke | mbx_smoke | 53.000s | 893.116us | 1 | 1 | 100.00 |
| V1 | csr_hw_reset | mbx_csr_hw_reset | 4.000s | 23.843us | 1 | 1 | 100.00 |
| V1 | csr_rw | mbx_csr_rw | 4.000s | 13.443us | 1 | 1 | 100.00 |
| V1 | csr_bit_bash | mbx_csr_bit_bash | 5.000s | 1.303ms | 1 | 1 | 100.00 |
| V1 | csr_aliasing | mbx_csr_aliasing | 4.000s | 16.027us | 1 | 1 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | mbx_csr_mem_rw_with_rand_reset | 4.000s | 6.741us | 0 | 1 | 0.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | mbx_csr_rw | 4.000s | 13.443us | 1 | 1 | 100.00 |
| mbx_csr_aliasing | 4.000s | 16.027us | 1 | 1 | 100.00 | ||
| V1 | TOTAL | 5 | 6 | 83.33 | |||
| V2 | mbx_stress | mbx_stress | 1.417m | 1.618ms | 1 | 1 | 100.00 |
| mbx_stress_zero_delays | 1.083m | 2.581ms | 1 | 1 | 100.00 | ||
| V2 | mbx_imbx_oob | mbx_imbx_oob | 45.000s | 8.040ms | 1 | 1 | 100.00 |
| V2 | alert_test | mbx_alert_test | 6.000s | 13.347us | 1 | 1 | 100.00 |
| V2 | tl_d_oob_addr_access | mbx_tl_errors | 6.000s | 1.149us | 0 | 1 | 0.00 |
| V2 | tl_d_illegal_access | mbx_tl_errors | 6.000s | 1.149us | 0 | 1 | 0.00 |
| V2 | tl_d_outstanding_access | mbx_csr_hw_reset | 4.000s | 23.843us | 1 | 1 | 100.00 |
| mbx_csr_rw | 4.000s | 13.443us | 1 | 1 | 100.00 | ||
| mbx_csr_aliasing | 4.000s | 16.027us | 1 | 1 | 100.00 | ||
| mbx_same_csr_outstanding | 5.000s | 17.524us | 1 | 1 | 100.00 | ||
| V2 | tl_d_partial_access | mbx_csr_hw_reset | 4.000s | 23.843us | 1 | 1 | 100.00 |
| mbx_csr_rw | 4.000s | 13.443us | 1 | 1 | 100.00 | ||
| mbx_csr_aliasing | 4.000s | 16.027us | 1 | 1 | 100.00 | ||
| mbx_same_csr_outstanding | 5.000s | 17.524us | 1 | 1 | 100.00 | ||
| V2 | TOTAL | 5 | 6 | 83.33 | |||
| V2S | tl_intg_err | mbx_sec_cm | 8.000s | 13.601us | 1 | 1 | 100.00 |
| mbx_tl_intg_err | 5.000s | 22.085us | 0 | 1 | 0.00 | ||
| V2S | TOTAL | 1 | 2 | 50.00 | |||
| TOTAL | 11 | 14 | 78.57 |
UVM_ERROR (tl_host_seq.sv:55) sequencer [tl_seq] fail to find matching req for rsp[*]: a_addr = * a_data = * a_mask = * a_size = * a_param = * a_source = * a_opcode = PutPartialData a_user = * d_data = * d_size = * d_param = * d_source = * d_opcode = AccessAckData d_error = * d_user = * d_sink = * req_abort_after_a_valid_len = * rsp_abort_after_d_valid_len = * req_completed = * rsp_completed = * has 2 failures:
Test mbx_tl_errors has 1 failures.
0.mbx_tl_errors.98956651859544591904320916053632986632493957887960185954269304878117805217673
Line 82, in log /nightly/runs/scratch/master/mbx-sim-xcelium/0.mbx_tl_errors/latest/run.log
UVM_ERROR @ 1148847 ps: (tl_host_seq.sv:55) uvm_test_top.env.m_tl_agent_mbx_mem_reg_block.sequencer [uvm_test_top.env.virtual_sequencer._item.tl_seq] fail to find matching req for rsp[0]: a_addr = 0x55c1e53d a_data = 0x7711106b a_mask = 0x8 a_size = 0x2 a_param = 0x0 a_source = 0xcc a_opcode = PutPartialData a_user = 0x2598e d_data = 0x859ff334 d_size = 0x2 d_param = 0x0 d_source = 0x45 d_opcode = AccessAckData d_error = 0 d_user = 1111110100001 d_sink = 1 req_abort_after_a_valid_len = 1 rsp_abort_after_d_valid_len = 0 req_completed = 0 rsp_completed = 1
UVM_INFO @ 1148847 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test mbx_csr_mem_rw_with_rand_reset has 1 failures.
0.mbx_csr_mem_rw_with_rand_reset.48032477460490395459745789664170355382203240283740939639101916116820977429721
Line 83, in log /nightly/runs/scratch/master/mbx-sim-xcelium/0.mbx_csr_mem_rw_with_rand_reset/latest/run.log
UVM_ERROR @ 6740530 ps: (tl_host_seq.sv:55) uvm_test_top.env.m_tl_agent_mbx_mem_reg_block.sequencer [uvm_test_top.env.virtual_sequencer._item.tl_seq] fail to find matching req for rsp[0]: a_addr = 0x6d3f43dc a_data = 0x67485c95 a_mask = 0xf a_size = 0x2 a_param = 0x0 a_source = 0xdf a_opcode = PutPartialData a_user = 0x2ce8c d_data = 0x221ab74e d_size = 0x1 d_param = 0x0 d_source = 0x26 d_opcode = AccessAckData d_error = 0 d_user = 111101011110 d_sink = 1 req_abort_after_a_valid_len = 0 rsp_abort_after_d_valid_len = 0 req_completed = 0 rsp_completed = 1
UVM_INFO @ 6740530 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (tl_host_seq.sv:55) sequencer [tl_seq] fail to find matching req for rsp[*]: a_addr = * a_data = * a_mask = * a_size = * a_param = * a_source = * a_opcode = PutPartialData a_user = * d_data = * d_size = * d_param = * d_source = * d_opcode = AccessAck d_error = * d_user = * d_sink = * req_abort_after_a_valid_len = * rsp_abort_after_d_valid_len = * req_completed = * rsp_completed = * has 1 failures:
0.mbx_tl_intg_err.23594268299657403763953200287819771784733041674957572248271045248100647492389
Line 102, in log /nightly/runs/scratch/master/mbx-sim-xcelium/0.mbx_tl_intg_err/latest/run.log
UVM_ERROR @ 22084990 ps: (tl_host_seq.sv:55) uvm_test_top.env.m_tl_agent_mbx_mem_reg_block.sequencer [uvm_test_top.env.virtual_sequencer._item.tl_seq] fail to find matching req for rsp[0]: a_addr = 0x7a5c2f80 a_data = 0xc83fde7 a_mask = 0x7 a_size = 0x2 a_param = 0x0 a_source = 0x5f a_opcode = PutPartialData a_user = 0x267d5 d_data = 0x5bf12fa3 d_size = 0x0 d_param = 0x0 d_source = 0xd2 d_opcode = AccessAck d_error = 0 d_user = 11110111000010 d_sink = 1 req_abort_after_a_valid_len = 0 rsp_abort_after_d_valid_len = 0 req_completed = 0 rsp_completed = 1
UVM_INFO @ 22084990 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---