OTBN Simulation Results

Thursday April 03 2025 17:08:38 UTC

GitHub Revision: aeb7302

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	otbn_smoke	10.000s	39.669us	1	1	100.00
V1	single_binary	otbn_single	9.000s	16.267us	1	1	100.00
V1	csr_hw_reset	otbn_csr_hw_reset	5.000s	50.660us	1	1	100.00
V1	csr_rw	otbn_csr_rw	5.000s	36.265us	1	1	100.00
V1	csr_bit_bash	otbn_csr_bit_bash	6.000s	39.131us	1	1	100.00
V1	csr_aliasing	otbn_csr_aliasing	5.000s	37.623us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	otbn_csr_mem_rw_with_rand_reset	7.000s	89.683us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	otbn_csr_rw	5.000s	36.265us	1	1	100.00
		otbn_csr_aliasing	5.000s	37.623us	1	1	100.00
V1	mem_walk	otbn_mem_walk	32.000s	11.900ms	1	1	100.00
V1	mem_partial_access	otbn_mem_partial_access	10.000s	362.149us	1	1	100.00
V1		TOTAL			9	9	100.00
V2	reset_recovery	otbn_reset	33.000s	326.499us	1	1	100.00
V2	multi_error	otbn_multi_err	58.000s	223.252us	1	1	100.00
V2	back_to_back	otbn_multi	1.000m	1.267ms	1	1	100.00
V2	stress_all	otbn_stress_all	58.000s	245.406us	1	1	100.00
V2	lc_escalation	otbn_escalate	8.000s	63.776us	1	1	100.00
V2	zero_state_err_urnd	otbn_zero_state_err_urnd	10.000s	64.308us	1	1	100.00
V2	sw_errs_fatal_chk	otbn_sw_errs_fatal_chk	10.000s	72.080us	1	1	100.00
V2	alert_test	otbn_alert_test	6.000s	30.732us	1	1	100.00
V2	intr_test	otbn_intr_test	5.000s	14.253us	1	1	100.00
V2	tl_d_oob_addr_access	otbn_tl_errors	6.000s	45.928us	1	1	100.00
V2	tl_d_illegal_access	otbn_tl_errors	6.000s	45.928us	1	1	100.00
V2	tl_d_outstanding_access	otbn_csr_hw_reset	5.000s	50.660us	1	1	100.00
		otbn_csr_rw	5.000s	36.265us	1	1	100.00
		otbn_csr_aliasing	5.000s	37.623us	1	1	100.00
		otbn_same_csr_outstanding	6.000s	15.895us	1	1	100.00
V2	tl_d_partial_access	otbn_csr_hw_reset	5.000s	50.660us	1	1	100.00
		otbn_csr_rw	5.000s	36.265us	1	1	100.00
		otbn_csr_aliasing	5.000s	37.623us	1	1	100.00
		otbn_same_csr_outstanding	6.000s	15.895us	1	1	100.00
V2		TOTAL			11	11	100.00
V2S	mem_integrity	otbn_imem_err	12.000s	75.083us	1	1	100.00
		otbn_dmem_err	11.000s	74.769us	1	1	100.00
V2S	internal_integrity	otbn_alu_bignum_mod_err	9.000s	53.814us	1	1	100.00
		otbn_controller_ispr_rdata_err	15.000s	79.969us	1	1	100.00
		otbn_mac_bignum_acc_err	10.000s	286.542us	1	1	100.00
		otbn_urnd_err	8.000s	29.365us	1	1	100.00
V2S	illegal_bus_access	otbn_illegal_mem_acc	7.000s	31.053us	1	1	100.00
V2S	otbn_mem_gnt_acc_err	otbn_mem_gnt_acc_err	8.000s	34.427us	1	1	100.00
V2S	otbn_non_sec_partial_wipe	otbn_partial_wipe	6.000s	9.251us	0	1	0.00
V2S	tl_intg_err	otbn_sec_cm	12.000s	34.169us	0	1	0.00
		otbn_tl_intg_err	17.000s	98.597us	1	1	100.00
V2S	passthru_mem_tl_intg_err	otbn_passthru_mem_tl_intg_err	14.000s	574.529us	1	1	100.00
V2S	prim_fsm_check	otbn_sec_cm	12.000s	34.169us	0	1	0.00
V2S	prim_count_check	otbn_sec_cm	12.000s	34.169us	0	1	0.00
V2S	sec_cm_mem_scramble	otbn_smoke	10.000s	39.669us	1	1	100.00
V2S	sec_cm_data_mem_integrity	otbn_dmem_err	11.000s	74.769us	1	1	100.00
V2S	sec_cm_instruction_mem_integrity	otbn_imem_err	12.000s	75.083us	1	1	100.00
V2S	sec_cm_bus_integrity	otbn_tl_intg_err	17.000s	98.597us	1	1	100.00
V2S	sec_cm_controller_fsm_global_esc	otbn_escalate	8.000s	63.776us	1	1	100.00
V2S	sec_cm_controller_fsm_local_esc	otbn_imem_err	12.000s	75.083us	1	1	100.00
		otbn_dmem_err	11.000s	74.769us	1	1	100.00
		otbn_zero_state_err_urnd	10.000s	64.308us	1	1	100.00
		otbn_illegal_mem_acc	7.000s	31.053us	1	1	100.00
		otbn_sec_cm	12.000s	34.169us	0	1	0.00
V2S	sec_cm_controller_fsm_sparse	otbn_sec_cm	12.000s	34.169us	0	1	0.00
V2S	sec_cm_scramble_key_sideload	otbn_single	9.000s	16.267us	1	1	100.00
V2S	sec_cm_scramble_ctrl_fsm_local_esc	otbn_imem_err	12.000s	75.083us	1	1	100.00
		otbn_dmem_err	11.000s	74.769us	1	1	100.00
		otbn_zero_state_err_urnd	10.000s	64.308us	1	1	100.00
		otbn_illegal_mem_acc	7.000s	31.053us	1	1	100.00
		otbn_sec_cm	12.000s	34.169us	0	1	0.00
V2S	sec_cm_scramble_ctrl_fsm_sparse	otbn_sec_cm	12.000s	34.169us	0	1	0.00
V2S	sec_cm_start_stop_ctrl_fsm_global_esc	otbn_escalate	8.000s	63.776us	1	1	100.00
V2S	sec_cm_start_stop_ctrl_fsm_local_esc	otbn_imem_err	12.000s	75.083us	1	1	100.00
		otbn_dmem_err	11.000s	74.769us	1	1	100.00
		otbn_zero_state_err_urnd	10.000s	64.308us	1	1	100.00
		otbn_illegal_mem_acc	7.000s	31.053us	1	1	100.00
		otbn_sec_cm	12.000s	34.169us	0	1	0.00
V2S	sec_cm_start_stop_ctrl_fsm_sparse	otbn_sec_cm	12.000s	34.169us	0	1	0.00
V2S	sec_cm_data_reg_sw_sca	otbn_single	9.000s	16.267us	1	1	100.00
V2S	sec_cm_ctrl_redun	otbn_ctrl_redun	7.000s	42.472us	1	1	100.00
V2S	sec_cm_pc_ctrl_flow_redun	otbn_pc_ctrl_flow_redun	7.000s	38.900us	1	1	100.00
V2S	sec_cm_rnd_bus_consistency	otbn_rnd_sec_cm	17.000s	441.526us	1	1	100.00
V2S	sec_cm_rnd_rng_digest	otbn_rnd_sec_cm	17.000s	441.526us	1	1	100.00
V2S	sec_cm_rf_base_data_reg_sw_integrity	otbn_rf_base_intg_err	8.000s	17.198us	1	1	100.00
V2S	sec_cm_rf_base_data_reg_sw_glitch_detect	otbn_sec_cm	12.000s	34.169us	0	1	0.00
V2S	sec_cm_stack_wr_ptr_ctr_redun	otbn_sec_cm	12.000s	34.169us	0	1	0.00
V2S	sec_cm_rf_bignum_data_reg_sw_integrity	otbn_rf_bignum_intg_err	10.000s	57.662us	1	1	100.00
V2S	sec_cm_rf_bignum_data_reg_sw_glitch_detect	otbn_sec_cm	12.000s	34.169us	0	1	0.00
V2S	sec_cm_loop_stack_ctr_redun	otbn_sec_cm	12.000s	34.169us	0	1	0.00
V2S	sec_cm_loop_stack_addr_integrity	otbn_stack_addr_integ_chk	7.000s	43.287us	1	1	100.00
V2S	sec_cm_call_stack_addr_integrity	otbn_stack_addr_integ_chk	7.000s	43.287us	1	1	100.00
V2S	sec_cm_start_stop_ctrl_state_consistency	otbn_sec_wipe_err	7.000s	13.806us	1	1	100.00
V2S	sec_cm_data_mem_sec_wipe	otbn_single	9.000s	16.267us	1	1	100.00
V2S	sec_cm_instruction_mem_sec_wipe	otbn_single	9.000s	16.267us	1	1	100.00
V2S	sec_cm_data_reg_sw_sec_wipe	otbn_single	9.000s	16.267us	1	1	100.00
V2S	sec_cm_write_mem_integrity	otbn_multi	1.000m	1.267ms	1	1	100.00
V2S	sec_cm_ctrl_flow_count	otbn_single	9.000s	16.267us	1	1	100.00
V2S	sec_cm_ctrl_flow_sca	otbn_single	9.000s	16.267us	1	1	100.00
V2S	sec_cm_data_mem_sw_noaccess	otbn_sw_no_acc	10.000s	26.338us	1	1	100.00
V2S	sec_cm_key_sideload	otbn_single	9.000s	16.267us	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	otbn_sec_cm	12.000s	34.169us	0	1	0.00
V2S		TOTAL			18	20	90.00
V3	stress_all_with_rand_reset	otbn_stress_all_with_rand_reset	2.117m	779.638us	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			38	41	92.68

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:908) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:

  • Test otbn_stress_all_with_rand_reset has 1 failures.

    • 0.otbn_stress_all_with_rand_reset.55046922735002222367612573546772233656233164762576551638751613630885240907104
      Line 154, in log /nightly/runs/scratch/master/otbn-sim-xcelium/0.otbn_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 779638125 ps: (cip_base_vseq.sv:908) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 779638125 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_dv_otbn_sva_*/otbn_idle_checker.sv,171): Assertion NotRunningWhenLocked_A has failed has 1 failures:

  • Test otbn_partial_wipe has 1 failures.

    • 0.otbn_partial_wipe.80725179063312109258783318485803193656052144517733382423088109170445455009379
      Line 100, in log /nightly/runs/scratch/master/otbn-sim-xcelium/0.otbn_partial_wipe/latest/run.log

        xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_dv_otbn_sva_0.1/otbn_idle_checker.sv,171): (time 9251121 PS) Assertion tb.dut.idle_checker.NotRunningWhenLocked_A has failed
        UVM_ERROR @   9251121 ps: (otbn_idle_checker.sv:171) [ASSERT FAILED] NotRunningWhenLocked_A
        UVM_INFO @   9251121 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_*/rtl/otbn.sv,1383): Assertion ErrBitsKnown_A has failed has 1 failures:

  • Test otbn_sec_cm has 1 failures.

    • 0.otbn_sec_cm.88055361838827322576653658087508798989331840783924406900130136150840848856376
      Line 121, in log /nightly/runs/scratch/master/otbn-sim-xcelium/0.otbn_sec_cm/latest/run.log

        xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1383): (time 34168918 PS) Assertion tb.dut.ErrBitsKnown_A has failed
        xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,960): (time 34168918 PS) Assertion tb.dut.u_otbn_core.ErrBitsKnown_A has failed
        UVM_ERROR @  34168918 ps: (otbn.sv:1383) [ASSERT FAILED] ErrBitsKnown_A
        UVM_INFO @  34168918 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---