RV_TIMER Simulation Results

Thursday April 03 2025 17:08:38 UTC

GitHub Revision: aeb7302

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	random	rv_timer_random	30.980s	28.277ms	1	1	100.00
V1	csr_hw_reset	rv_timer_csr_hw_reset	1.480s	26.701us	1	1	100.00
V1	csr_rw	rv_timer_csr_rw	1.750s	60.082us	1	1	100.00
V1	csr_bit_bash	rv_timer_csr_bit_bash	2.770s	1.686ms	1	1	100.00
V1	csr_aliasing	rv_timer_csr_aliasing	1.970s	102.823us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	rv_timer_csr_mem_rw_with_rand_reset	1.480s	59.226us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rv_timer_csr_rw	1.750s	60.082us	1	1	100.00
		rv_timer_csr_aliasing	1.970s	102.823us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	random_reset	rv_timer_random_reset	25.340s	16.352ms	1	1	100.00
V2	disabled	rv_timer_disabled	1.762m	367.468ms	1	1	100.00
V2	cfg_update_on_fly	rv_timer_cfg_update_on_fly	1.349m	134.929ms	1	1	100.00
V2	no_interrupt_test	rv_timer_cfg_update_on_fly	1.349m	134.929ms	1	1	100.00
V2	stress	rv_timer_stress_all	7.144m	2.128s	1	1	100.00
V2	intr_test	rv_timer_intr_test	1.530s	24.435us	1	1	100.00
V2	tl_d_oob_addr_access	rv_timer_tl_errors	2.510s	34.840us	1	1	100.00
V2	tl_d_illegal_access	rv_timer_tl_errors	2.510s	34.840us	1	1	100.00
V2	tl_d_outstanding_access	rv_timer_csr_hw_reset	1.480s	26.701us	1	1	100.00
		rv_timer_csr_rw	1.750s	60.082us	1	1	100.00
		rv_timer_csr_aliasing	1.970s	102.823us	1	1	100.00
		rv_timer_same_csr_outstanding	1.770s	23.063us	1	1	100.00
V2	tl_d_partial_access	rv_timer_csr_hw_reset	1.480s	26.701us	1	1	100.00
		rv_timer_csr_rw	1.750s	60.082us	1	1	100.00
		rv_timer_csr_aliasing	1.970s	102.823us	1	1	100.00
		rv_timer_same_csr_outstanding	1.770s	23.063us	1	1	100.00
V2		TOTAL			7	7	100.00
V2S	tl_intg_err	rv_timer_sec_cm	1.980s	1.132ms	1	1	100.00
		rv_timer_tl_intg_err	2.410s	421.615us	1	1	100.00
V2S	sec_cm_bus_integrity	rv_timer_tl_intg_err	2.410s	421.615us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	rv_timer_stress_all_with_rand_reset	13.010s	1.734ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			16	16	100.00