SPI_HOST Simulation Results

Thursday April 03 2025 17:08:38 UTC

GitHub Revision: aeb7302

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_host_smoke	1.150m	15.886ms	1	1	100.00
V1	csr_hw_reset	spi_host_csr_hw_reset	4.000s	28.072us	1	1	100.00
V1	csr_rw	spi_host_csr_rw	4.000s	44.623us	1	1	100.00
V1	csr_bit_bash	spi_host_csr_bit_bash	5.000s	896.750us	1	1	100.00
V1	csr_aliasing	spi_host_csr_aliasing	4.000s	35.537us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_host_csr_mem_rw_with_rand_reset	4.000s	24.714us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_host_csr_rw	4.000s	44.623us	1	1	100.00
		spi_host_csr_aliasing	4.000s	35.537us	1	1	100.00
V1	mem_walk	spi_host_mem_walk	4.000s	16.893us	1	1	100.00
V1	mem_partial_access	spi_host_mem_partial_access	4.000s	25.295us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	performance	spi_host_performance	5.000s	33.347us	1	1	100.00
V2	error_event_intr	spi_host_overflow_underflow	10.000s	309.392us	1	1	100.00
		spi_host_error_cmd	4.000s	17.914us	1	1	100.00
		spi_host_event	2.617m	16.754ms	1	1	100.00
V2	clock_rate	spi_host_speed	6.000s	574.982us	1	1	100.00
V2	speed	spi_host_speed	6.000s	574.982us	1	1	100.00
V2	chip_select_timing	spi_host_speed	6.000s	574.982us	1	1	100.00
V2	sw_reset	spi_host_sw_reset	11.000s	416.489us	1	1	100.00
V2	passthrough_mode	spi_host_passthrough_mode	4.000s	215.209us	1	1	100.00
V2	cpol_cpha	spi_host_speed	6.000s	574.982us	1	1	100.00
V2	full_cycle	spi_host_speed	6.000s	574.982us	1	1	100.00
V2	duplex	spi_host_smoke	1.150m	15.886ms	1	1	100.00
V2	tx_rx_only	spi_host_smoke	1.150m	15.886ms	1	1	100.00
V2	stress_all	spi_host_stress_all	2.450m	45.907ms	1	1	100.00
V2	spien	spi_host_spien	24.000s	8.733ms	1	1	100.00
V2	stall	spi_host_status_stall	26.000s	5.360ms	1	1	100.00
V2	Idlecsbactive	spi_host_idlecsbactive	5.000s	73.825us	1	1	100.00
V2	data_fifo_status	spi_host_overflow_underflow	10.000s	309.392us	1	1	100.00
V2	alert_test	spi_host_alert_test	5.000s	15.284us	1	1	100.00
V2	intr_test	spi_host_intr_test	4.000s	16.685us	1	1	100.00
V2	tl_d_oob_addr_access	spi_host_tl_errors	5.000s	78.506us	1	1	100.00
V2	tl_d_illegal_access	spi_host_tl_errors	5.000s	78.506us	1	1	100.00
V2	tl_d_outstanding_access	spi_host_csr_hw_reset	4.000s	28.072us	1	1	100.00
		spi_host_csr_rw	4.000s	44.623us	1	1	100.00
		spi_host_csr_aliasing	4.000s	35.537us	1	1	100.00
		spi_host_same_csr_outstanding	4.000s	23.875us	1	1	100.00
V2	tl_d_partial_access	spi_host_csr_hw_reset	4.000s	28.072us	1	1	100.00
		spi_host_csr_rw	4.000s	44.623us	1	1	100.00
		spi_host_csr_aliasing	4.000s	35.537us	1	1	100.00
		spi_host_same_csr_outstanding	4.000s	23.875us	1	1	100.00
V2		TOTAL			15	15	100.00
V2S	tl_intg_err	spi_host_tl_intg_err	4.000s	231.717us	1	1	100.00
		spi_host_sec_cm	4.000s	79.651us	1	1	100.00
V2S	sec_cm_bus_integrity	spi_host_tl_intg_err	4.000s	231.717us	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_host_upper_range_clkdiv	12.950m	91.670ms	1	1	100.00
		TOTAL			26	26	100.00