UART Simulation Results

Thursday April 03 2025 17:08:38 UTC

GitHub Revision: aeb7302

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	2.520s	431.272us	1	1	100.00
V1	csr_hw_reset	uart_csr_hw_reset	1.500s	58.182us	1	1	100.00
V1	csr_rw	uart_csr_rw	1.580s	24.269us	1	1	100.00
V1	csr_bit_bash	uart_csr_bit_bash	2.700s	174.822us	1	1	100.00
V1	csr_aliasing	uart_csr_aliasing	1.760s	61.624us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	1.860s	110.466us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	1.580s	24.269us	1	1	100.00
		uart_csr_aliasing	1.760s	61.624us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	base_random_seq	uart_tx_rx	28.530s	90.371ms	1	1	100.00
V2	parity	uart_smoke	2.520s	431.272us	1	1	100.00
		uart_tx_rx	28.530s	90.371ms	1	1	100.00
V2	parity_error	uart_intr	50.590s	45.702ms	1	1	100.00
		uart_rx_parity_err	2.042m	136.453ms	1	1	100.00
V2	watermark	uart_tx_rx	28.530s	90.371ms	1	1	100.00
		uart_intr	50.590s	45.702ms	1	1	100.00
V2	fifo_full	uart_fifo_full	44.550s	25.256ms	1	1	100.00
V2	fifo_overflow	uart_fifo_overflow	13.690s	49.933ms	1	1	100.00
V2	fifo_reset	uart_fifo_reset	24.130s	85.480ms	1	1	100.00
V2	rx_frame_err	uart_intr	50.590s	45.702ms	1	1	100.00
V2	rx_break_err	uart_intr	50.590s	45.702ms	1	1	100.00
V2	rx_timeout	uart_intr	50.590s	45.702ms	1	1	100.00
V2	perf	uart_perf	1.437m	20.149ms	1	1	100.00
V2	sys_loopback	uart_loopback	6.090s	5.755ms	1	1	100.00
V2	line_loopback	uart_loopback	6.090s	5.755ms	1	1	100.00
V2	rx_noise_filter	uart_noise_filter	17.220s	12.995ms	1	1	100.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	3.230s	2.455ms	1	1	100.00
V2	tx_overide	uart_tx_ovrd	3.120s	1.359ms	1	1	100.00
V2	rx_oversample	uart_rx_oversample	11.220s	6.647ms	1	1	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	5.140m	98.306ms	1	1	100.00
V2	stress_all	uart_stress_all	2.042m	355.036ms	1	1	100.00
V2	alert_test	uart_alert_test	1.470s	84.246us	1	1	100.00
V2	intr_test	uart_intr_test	1.590s	49.559us	1	1	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	2.060s	100.723us	1	1	100.00
V2	tl_d_illegal_access	uart_tl_errors	2.060s	100.723us	1	1	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	1.500s	58.182us	1	1	100.00
		uart_csr_rw	1.580s	24.269us	1	1	100.00
		uart_csr_aliasing	1.760s	61.624us	1	1	100.00
		uart_same_csr_outstanding	1.820s	26.576us	1	1	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	1.500s	58.182us	1	1	100.00
		uart_csr_rw	1.580s	24.269us	1	1	100.00
		uart_csr_aliasing	1.760s	61.624us	1	1	100.00
		uart_same_csr_outstanding	1.820s	26.576us	1	1	100.00
V2		TOTAL			18	18	100.00
V2S	tl_intg_err	uart_sec_cm	2.000s	240.677us	1	1	100.00
		uart_tl_intg_err	2.000s	92.205us	1	1	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	2.000s	92.205us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	32.510s	26.277ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			27	27	100.00