CHIP Simulation Results

Thursday April 03 2025 17:08:38 UTC

GitHub Revision: `aeb7302`

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	chip_sw_uart_tx_rx	chip_sw_uart_tx_rx	2.205m		0	1	0.00
V1	chip_sw_uart_rx_overflow	chip_sw_uart_tx_rx	2.205m		0	1	0.00
V1	chip_sw_uart_rand_baudrate	chip_sw_uart_rand_baudrate	2.155m		0	1	0.00
V1	chip_sw_uart_tx_rx_alt_clk_freq	chip_sw_uart_tx_rx_alt_clk_freq	2.240m		0	1	0.00
		chip_sw_uart_tx_rx_alt_clk_freq_low_speed	2.290m		0	1	0.00
V1	chip_sw_gpio_out	chip_sw_gpio	7.291m	6.315ms	1	1	100.00
V1	chip_sw_gpio_in	chip_sw_gpio	7.291m	6.315ms	1	1	100.00
V1	chip_sw_gpio_irq	chip_sw_gpio	7.291m	6.315ms	1	1	100.00
V1	chip_sw_example_tests	chip_sw_example_rom	1.187m		0	1	0.00
		chip_sw_example_manufacturer	1.170m		0	1	0.00
		chip_sw_example_concurrency	4.306m	5.488ms	1	1	100.00
		chip_sw_uart_smoketest_signed	11.109s		0	1	0.00
V1	csr_bit_bash	chip_csr_bit_bash	9.730s		0	1	0.00
V1	csr_aliasing	chip_csr_aliasing	9.640s		0	1	0.00
V1	regwen_csr_and_corresponding_lockable_csr	chip_csr_aliasing	9.640s		0	1	0.00
V1	xbar_smoke	xbar_smoke	18.420s	57.147us	1	1	100.00
V1		TOTAL			3	12	25.00
V2	chip_sw_spi_device_flash_mode	chip_sw_uart_tx_rx_bootstrap	2.189m		0	1	0.00
V2	chip_sw_spi_device_pass_through	chip_sw_spi_device_pass_through	7.727m	7.110ms	1	1	100.00
V2	chip_sw_spi_device_pass_through_collision	chip_sw_spi_device_pass_through_collision	4.258m	4.323ms	0	1	0.00
V2	chip_sw_spi_device_tpm	chip_sw_spi_device_tpm	1.754m		0	1	0.00
V2	chip_sw_spi_host_tx_rx	chip_sw_spi_host_tx_rx	1.972m		0	1	0.00
V2	chip_sw_i2c_host_tx_rx	chip_sw_i2c_host_tx_rx	1.955m		0	1	0.00
V2	chip_sw_i2c_device_tx_rx	chip_sw_i2c_device_tx_rx	1.854m		0	1	0.00
V2	chip_pin_mux	chip_padctrl_attributes	3.380s		0	1	0.00
V2	chip_padctrl_attributes	chip_padctrl_attributes	3.380s		0	1	0.00
V2	chip_sw_sleep_pin_wake	chip_sw_sleep_pin_wake	2.289m		0	1	0.00
V2	chip_sw_sleep_pin_retention	chip_sw_sleep_pin_retention	2.289m		0	1	0.00
V2	chip_sw_data_integrity	chip_sw_data_integrity_escalation	2.390m		0	1	0.00
V2	chip_sw_instruction_integrity	chip_sw_data_integrity_escalation	2.390m		0	1	0.00
V2	chip_jtag_csr_rw	chip_jtag_csr_rw	2.515m	3.407ms	0	1	0.00
V2	chip_jtag_mem_access	chip_jtag_mem_access	3.193m	3.881ms	0	1	0.00
V2	chip_rv_dm_ndm_reset_req	chip_rv_dm_ndm_reset_req	5.343m	7.464ms	1	1	100.00
V2	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	12.023s		0	1	0.00
V2	chip_rv_dm_access_after_wakeup	chip_sw_rv_dm_access_after_wakeup	13.066s		0	1	0.00
V2	chip_rv_dm_lc_disabled	chip_rv_dm_lc_disabled	13.610m	28.796ms	1	1	100.00
V2	chip_sw_timer	chip_sw_rv_timer_irq	6.045m	5.799ms	1	1	100.00
V2	chip_sw_aon_timer_wakeup_irq	chip_sw_aon_timer_irq	19.432m	18.016ms	0	1	0.00
V2	chip_sw_aon_timer_wdog_bark_irq	chip_sw_aon_timer_irq	19.432m	18.016ms	0	1	0.00
V2	chip_sw_aon_timer_wdog_lc_escalate	chip_sw_aon_timer_wdog_lc_escalate	12.027s		0	1	0.00
V2	chip_sw_aon_timer_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	20.033s		0	1	0.00
V2	chip_sw_aon_timer_sleep_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	20.033s		0	1	0.00
V2	chip_sw_aon_timer_sleep_wdog_sleep_pause	chip_sw_aon_timer_sleep_wdog_sleep_pause	31.101s		0	1	0.00
V2	chip_sw_plic_all_irqs	chip_plic_all_irqs	11.028s		0	1	0.00
V2	chip_sw_plic_sw_irq	chip_sw_plic_sw_irq	4.317m	5.502ms	1	1	100.00
V2	chip_sw_clkmgr_idle_trans	chip_sw_otbn_randomness	5.476m	4.564ms	1	1	100.00
		chip_sw_aes_idle	4.722m	4.123ms	1	1	100.00
		chip_sw_hmac_enc_idle	4.123m	6.014ms	1	1	100.00
		chip_sw_kmac_idle	3.685m	4.006ms	1	1	100.00
V2	chip_sw_clkmgr_off_trans	chip_sw_clkmgr_off_aes_trans	15.040s		0	1	0.00
		chip_sw_clkmgr_off_hmac_trans	12.021s		0	1	0.00
		chip_sw_clkmgr_off_kmac_trans	14.029s		0	1	0.00
		chip_sw_clkmgr_off_otbn_trans	14.040s		0	1	0.00
V2	chip_sw_clkmgr_div	chip_sw_clkmgr_external_clk_src_for_lc	14.065s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	12.068s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	14.066s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	13.060s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	12.047s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	13.072s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	11.031s		0	1	0.00
V2	chip_sw_clkmgr_external_clk_src_for_lc	chip_sw_clkmgr_external_clk_src_for_lc	14.065s		0	1	0.00
V2	chip_sw_clkmgr_external_clk_src_for_sw	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	12.068s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	14.066s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	13.060s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	12.047s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	13.072s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	11.031s		0	1	0.00
V2	chip_sw_clkmgr_jitter	chip_sw_otbn_ecdsa_op_irq_jitter_en	42.072s		0	1	0.00
		chip_sw_aes_enc_jitter_en	45.970s	10.160us	0	1	0.00
		chip_sw_hmac_enc_jitter_en	47.470s	10.180us	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	49.600s	10.240us	0	1	0.00
		chip_sw_kmac_mode_kmac_jitter_en	49.920s	10.280us	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	12.031s		0	1	0.00
		chip_sw_clkmgr_jitter	3.710m	4.775ms	1	1	100.00
V2	chip_sw_clkmgr_extended_range	chip_sw_clkmgr_jitter_reduced_freq	3.010m	3.273ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq	16.039s		0	1	0.00
		chip_sw_aes_enc_jitter_en_reduced_freq	50.780s	10.320us	0	1	0.00
		chip_sw_hmac_enc_jitter_en_reduced_freq	46.040s	10.200us	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en_reduced_freq	47.130s	10.140us	0	1	0.00
		chip_sw_kmac_mode_kmac_jitter_en_reduced_freq	48.850s	10.220us	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq	51.750s	10.340us	0	1	0.00
		chip_sw_csrng_edn_concurrency_reduced_freq	13.032s		0	1	0.00
V2	chip_sw_clkmgr_deep_sleep_frequency	chip_sw_ast_clk_outputs	13.045s		0	1	0.00
V2	chip_sw_clkmgr_sleep_frequency	chip_sw_clkmgr_sleep_frequency	12.051s		0	1	0.00
V2	chip_sw_clkmgr_reset_frequency	chip_sw_clkmgr_reset_frequency	12.056s		0	1	0.00
V2	chip_sw_clkmgr_escalation_reset	chip_sw_all_escalation_resets	15.027m	17.570ms	0	1	0.00
V2	chip_sw_pwrmgr_external_full_reset	chip_sw_pwrmgr_full_aon_reset	9.299m	12.863ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_all_reset_reqs	chip_sw_aon_timer_wdog_bite_reset	20.033s		0	1	0.00
V2	chip_sw_pwrmgr_wdog_reset	chip_sw_pwrmgr_wdog_reset	22.067s		0	1	0.00
V2	chip_sw_pwrmgr_aon_power_glitch_reset	chip_sw_pwrmgr_full_aon_reset	9.299m	12.863ms	1	1	100.00
V2	chip_sw_pwrmgr_main_power_glitch_reset	chip_sw_pwrmgr_main_power_glitch_reset	24.105s		0	1	0.00
V2	chip_sw_pwrmgr_random_sleep_power_glitch_reset	chip_sw_pwrmgr_random_sleep_power_glitch_reset	13.053s		0	1	0.00
V2	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	28.105s		0	1	0.00
V2	chip_sw_pwrmgr_sleep_power_glitch_reset	chip_sw_pwrmgr_sleep_power_glitch_reset	12.051s		0	1	0.00
V2	chip_sw_pwrmgr_sleep_disabled	chip_sw_pwrmgr_sleep_disabled	15.060s		0	1	0.00
V2	chip_sw_pwrmgr_escalation_reset	chip_sw_all_escalation_resets	15.027m	17.570ms	0	1	0.00
V2	chip_sw_rstmgr_sys_reset_info	chip_rv_dm_ndm_reset_req	5.343m	7.464ms	1	1	100.00
V2	chip_sw_rstmgr_cpu_info	chip_sw_rstmgr_cpu_info	5.495m	20.025ms	0	1	0.00
V2	chip_sw_rstmgr_sw_req_reset	chip_sw_rstmgr_sw_req	6.250m	6.445ms	1	1	100.00
V2	chip_sw_rstmgr_alert_info	chip_sw_rstmgr_alert_info	10.495m	30.016ms	0	1	0.00
V2	chip_sw_rstmgr_sw_rst	chip_sw_rstmgr_sw_rst	3.416m	5.173ms	1	1	100.00
V2	chip_sw_rstmgr_escalation_reset	chip_sw_all_escalation_resets	15.027m	17.570ms	0	1	0.00
V2	chip_sw_alert_handler_alerts	chip_sw_alert_test	16.014s		0	1	0.00
V2	chip_sw_alert_handler_escalations	chip_sw_alert_handler_escalation	12.011s		0	1	0.00
V2	chip_sw_all_escalation_resets	chip_sw_all_escalation_resets	15.027m	17.570ms	0	1	0.00
V2	chip_sw_alert_handler_irqs	chip_plic_all_irqs	11.028s		0	1	0.00
V2	chip_sw_alert_handler_entropy	chip_sw_alert_handler_entropy	11.019s		0	1	0.00
V2	chip_sw_alert_handler_crashdump	chip_sw_rstmgr_alert_info	10.495m	30.016ms	0	1	0.00
V2	chip_sw_alert_handler_ping_timeout	chip_sw_alert_handler_ping_timeout	19.015s		0	1	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_alerts	chip_sw_alert_handler_lpg_sleep_mode_alerts	13.030s		0	1	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_pings	chip_sw_alert_handler_lpg_sleep_mode_pings	14.029s		0	1	0.00
V2	chip_sw_alert_handler_lpg_clock_off	chip_sw_alert_handler_lpg_clkoff	17.030s		0	1	0.00
V2	chip_sw_alert_handler_lpg_reset_toggle	chip_sw_alert_handler_lpg_reset_toggle	17.038s		0	1	0.00
V2	chip_sw_alert_handler_reverse_ping_in_deep_sleep	chip_sw_alert_handler_reverse_ping_in_deep_sleep	18.015s		0	1	0.00
V2	chip_sw_lc_ctrl_alert_handler_escalation	chip_sw_alert_handler_escalation	12.011s		0	1	0.00
V2	chip_sw_lc_ctrl_jtag_access	chip_sw_lc_ctrl_transition	40.241s		0	1	0.00
V2	chip_sw_lc_ctrl_otp_hw_cfg	chip_sw_lc_ctrl_otp_hw_cfg	48.168s		0	1	0.00
V2	chip_sw_lc_ctrl_init	chip_sw_lc_ctrl_transition	40.241s		0	1	0.00
V2	chip_sw_lc_ctrl_transitions	chip_sw_lc_ctrl_transition	40.241s		0	1	0.00
V2	chip_sw_lc_ctrl_kmac_req	chip_sw_lc_ctrl_transition	40.241s		0	1	0.00
V2	chip_sw_lc_ctrl_key_div	chip_sw_keymgr_dpe_key_derivation_prod	5.812m	7.556ms	0	1	0.00
V2	chip_sw_lc_ctrl_broadcast	chip_sw_otp_ctrl_lc_signals_test_unlocked0	49.254s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_dev	35.223s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_prod	23.169s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_rma	30.256s		0	1	0.00
		chip_sw_lc_ctrl_transition	40.241s		0	1	0.00
		chip_sw_keymgr_dpe_key_derivation	7.576m	20.010ms	0	1	0.00
		chip_sw_rom_ctrl_integrity_check	8.597m	13.150ms	1	1	100.00
		chip_sw_sram_ctrl_execution_main	11.031s		0	1	0.00
		chip_prim_tl_access	3.782m	8.537ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_lc	14.065s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	12.068s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	14.066s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	13.060s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	12.047s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	13.072s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	11.031s		0	1	0.00
		chip_rv_dm_lc_disabled	13.610m	28.796ms	1	1	100.00
V2	chip_sw_aes_enc	chip_sw_aes_enc	4.811m	5.060ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	45.970s	10.160us	0	1	0.00
V2	chip_sw_aes_entropy	chip_sw_aes_entropy	3.862m	4.316ms	1	1	100.00
V2	chip_sw_aes_idle	chip_sw_aes_idle	4.722m	4.123ms	1	1	100.00
V2	chip_sw_hmac_enc	chip_sw_hmac_enc	4.936m	5.521ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	47.470s	10.180us	0	1	0.00
V2	chip_sw_hmac_idle	chip_sw_hmac_enc_idle	4.123m	6.014ms	1	1	100.00
V2	chip_sw_kmac_enc	chip_sw_kmac_mode_cshake	3.807m	4.388ms	1	1	100.00
		chip_sw_kmac_mode_kmac	4.753m	3.773ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	49.920s	10.280us	0	1	0.00
V2	chip_sw_kmac_app_keymgr	chip_sw_keymgr_dpe_key_derivation	7.576m	20.010ms	0	1	0.00
V2	chip_sw_kmac_app_lc	chip_sw_lc_ctrl_transition	40.241s		0	1	0.00
V2	chip_sw_kmac_app_rom	chip_sw_kmac_app_rom	38.210s	10.280us	0	1	0.00
V2	chip_sw_kmac_entropy	chip_sw_kmac_entropy	4.908m	5.440ms	1	1	100.00
V2	chip_sw_kmac_idle	chip_sw_kmac_idle	3.685m	4.006ms	1	1	100.00
V2	chip_sw_entropy_src_csrng	chip_sw_entropy_src_csrng	11.020s		0	1	0.00
V2	chip_sw_csrng_edn_cmd	chip_sw_entropy_src_csrng	11.020s		0	1	0.00
V2	chip_sw_csrng_fuse_en_sw_app_read	chip_sw_csrng_fuse_en_sw_app_read_test	12.015s		0	1	0.00
V2	chip_sw_csrng_known_answer_tests	chip_sw_csrng_kat_test	4.352m	4.528ms	1	1	100.00
V2	chip_sw_edn_entropy_reqs	chip_sw_csrng_edn_concurrency	12.022s		0	1	0.00
V2	chip_sw_keymgr_dpe_key_derivation	chip_sw_keymgr_dpe_key_derivation	7.576m	20.010ms	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	49.600s	10.240us	0	1	0.00
V2	chip_sw_otbn_op	chip_sw_otbn_ecdsa_op_irq	22.054s		0	1	0.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	42.072s		0	1	0.00
V2	chip_sw_otbn_rnd_entropy	chip_sw_otbn_randomness	5.476m	4.564ms	1	1	100.00
V2	chip_sw_otbn_urnd_entropy	chip_sw_otbn_randomness	5.476m	4.564ms	1	1	100.00
V2	chip_sw_otbn_idle	chip_sw_otbn_randomness	5.476m	4.564ms	1	1	100.00
V2	chip_sw_otbn_mem_scramble	chip_sw_otbn_mem_scramble	8.056m	5.677ms	1	1	100.00
V2	chip_sw_rom_access	chip_sw_rom_ctrl_integrity_check	8.597m	13.150ms	1	1	100.00
V2	chip_sw_rom_ctrl_integrity_check	chip_sw_rom_ctrl_integrity_check	8.597m	13.150ms	1	1	100.00
V2	chip_sw_sram_scrambled_access	chip_sw_sram_ctrl_scrambled_access	15.023s		0	1	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	12.031s		0	1	0.00
V2	chip_sw_sram_execution	chip_sw_sram_ctrl_execution_main	11.031s		0	1	0.00
V2	chip_sw_sram_lc_escalation	chip_sw_all_escalation_resets	15.027m	17.570ms	0	1	0.00
		chip_sw_data_integrity_escalation	2.390m		0	1	0.00
V2	chip_otp_ctrl_init	chip_sw_lc_ctrl_transition	40.241s		0	1	0.00
V2	chip_sw_otp_ctrl_keys	chip_sw_otbn_mem_scramble	8.056m	5.677ms	1	1	100.00
		chip_sw_keymgr_dpe_key_derivation	7.576m	20.010ms	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access	15.023s		0	1	0.00
		chip_sw_rv_core_ibex_icache_invalidate	3.791m	3.742ms	1	1	100.00
V2	chip_sw_otp_ctrl_entropy	chip_sw_otbn_mem_scramble	8.056m	5.677ms	1	1	100.00
		chip_sw_keymgr_dpe_key_derivation	7.576m	20.010ms	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access	15.023s		0	1	0.00
		chip_sw_rv_core_ibex_icache_invalidate	3.791m	3.742ms	1	1	100.00
V2	chip_sw_otp_ctrl_program	chip_sw_lc_ctrl_transition	40.241s		0	1	0.00
V2	chip_sw_otp_ctrl_program_error	chip_sw_lc_ctrl_program_error	14.051s		0	1	0.00
V2	chip_sw_otp_ctrl_hw_cfg	chip_sw_lc_ctrl_otp_hw_cfg	48.168s		0	1	0.00
V2	chip_sw_otp_ctrl_lc_signals	chip_sw_otp_ctrl_lc_signals_test_unlocked0	49.254s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_dev	35.223s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_prod	23.169s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_rma	30.256s		0	1	0.00
		chip_sw_lc_ctrl_transition	40.241s		0	1	0.00
		chip_prim_tl_access	3.782m	8.537ms	1	1	100.00
V2	chip_sw_otp_prim_tl_access	chip_prim_tl_access	3.782m	8.537ms	1	1	100.00
V2	chip_sw_otp_ctrl_nvm_cnt	chip_sw_otp_ctrl_nvm_cnt	16.156s		0	1	0.00
V2	chip_sw_otp_ctrl_sw_parts	chip_sw_otp_ctrl_sw_parts	22.165s		0	1	0.00
V2	chip_sw_ast_clk_outputs	chip_sw_ast_clk_outputs	13.045s		0	1	0.00
V2	chip_sw_ast_sys_clk_jitter	chip_sw_otbn_ecdsa_op_irq_jitter_en	42.072s		0	1	0.00
		chip_sw_aes_enc_jitter_en	45.970s	10.160us	0	1	0.00
		chip_sw_hmac_enc_jitter_en	47.470s	10.180us	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	49.600s	10.240us	0	1	0.00
		chip_sw_kmac_mode_kmac_jitter_en	49.920s	10.280us	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	12.031s		0	1	0.00
		chip_sw_clkmgr_jitter	3.710m	4.775ms	1	1	100.00
V2	chip_sw_soc_proxy_external_reset_requests	chip_sw_soc_proxy_smoketest	7.014m	6.279ms	1	1	100.00
V2	chip_sw_soc_proxy_external_irqs	chip_sw_soc_proxy_smoketest	7.014m	6.279ms	1	1	100.00
V2	chip_sw_soc_proxy_external_alerts	chip_sw_soc_proxy_external_alerts	5.077m	5.509ms	0	1	0.00
V2	chip_sw_soc_proxy_external_wakeup_requests	chip_sw_soc_proxy_external_wakeup	3.786m	4.571ms	1	1	100.00
V2	chip_sw_soc_proxy_gpios	chip_sw_soc_proxy_gpios	3.720m	4.313ms	1	1	100.00
V2	chip_sw_nmi_irq	chip_sw_rv_core_ibex_nmi_irq	6.755m	6.014ms	0	1	0.00
V2	chip_sw_rv_core_ibex_rnd	chip_sw_rv_core_ibex_rnd	4.493m	5.542ms	1	1	100.00
V2	chip_sw_rv_core_ibex_address_translation	chip_sw_rv_core_ibex_address_translation	3.671m	5.416ms	1	1	100.00
V2	chip_sw_rv_core_ibex_icache_scrambled_access	chip_sw_rv_core_ibex_icache_invalidate	3.791m	3.742ms	1	1	100.00
V2	chip_sw_rv_core_ibex_fault_dump	chip_sw_rstmgr_cpu_info	5.495m	20.025ms	0	1	0.00
V2	chip_sw_rv_core_ibex_double_fault	chip_sw_rstmgr_cpu_info	5.495m	20.025ms	0	1	0.00
V2	chip_sw_smoketest	chip_sw_aes_smoketest	3.104m	3.563ms	1	1	100.00
		chip_sw_aon_timer_smoketest	3.675m	5.324ms	1	1	100.00
		chip_sw_clkmgr_smoketest	2.816m	4.754ms	1	1	100.00
		chip_sw_csrng_smoketest	2.699m	3.535ms	1	1	100.00
		chip_sw_gpio_smoketest	2.852m	3.521ms	1	1	100.00
		chip_sw_hmac_smoketest	3.847m	5.068ms	1	1	100.00
		chip_sw_kmac_smoketest	3.301m	5.337ms	1	1	100.00
		chip_sw_otbn_smoketest	4.393m	4.658ms	1	1	100.00
		chip_sw_otp_ctrl_smoketest	3.231m	3.874ms	1	1	100.00
		chip_sw_rv_plic_smoketest	3.184m	4.337ms	1	1	100.00
		chip_sw_rv_timer_smoketest	3.651m	5.209ms	1	1	100.00
		chip_sw_rstmgr_smoketest	2.918m	4.535ms	1	1	100.00
		chip_sw_sram_ctrl_smoketest	2.772m	4.170ms	1	1	100.00
		chip_sw_uart_smoketest	2.946m	4.964ms	1	1	100.00
V2	chip_sw_rom_functests	rom_keymgr_functest	12.172s		0	1	0.00
V2	chip_sw_signed	chip_sw_uart_smoketest_signed	11.109s		0	1	0.00
V2	chip_sw_boot	chip_sw_uart_tx_rx_bootstrap	2.189m		0	1	0.00
V2	chip_sw_secure_boot	base_rom_e2e_smoke	12.024s		0	1	0.00
V2	chip_lc_scrap	chip_sw_lc_ctrl_rma_to_scrap	4.166m	5.548ms	1	1	100.00
		chip_sw_lc_ctrl_raw_to_scrap	4.007m	5.966ms	1	1	100.00
		chip_sw_lc_ctrl_test_locked0_to_scrap	4.464m	5.703ms	1	1	100.00
		chip_sw_lc_ctrl_rand_to_scrap	3.252m	6.173ms	1	1	100.00
V2	chip_lc_test_locked	chip_sw_lc_walkthrough_testunlocks	16.090s		0	1	0.00
		chip_rv_dm_lc_disabled	13.610m	28.796ms	1	1	100.00
V2	chip_sw_lc_walkthrough	chip_sw_lc_walkthrough_dev	28.156s		0	1	0.00
		chip_sw_lc_walkthrough_prod	29.161s		0	1	0.00
		chip_sw_lc_walkthrough_prodend	57.239s		0	1	0.00
		chip_sw_lc_walkthrough_rma	26.136s		0	1	0.00
		chip_sw_lc_walkthrough_testunlocks	16.090s		0	1	0.00
V2	chip_sw_lc_ctrl_volatile_raw_unlock	chip_sw_lc_ctrl_volatile_raw_unlock	16.097s		0	1	0.00
		chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	58.243s		0	1	0.00
		rom_volatile_raw_unlock	11.111s		0	1	0.00
V2	chip_sw_rom_raw_unlock	rom_raw_unlock	12.122s		0	1	0.00
V2	chip_sw_exit_test_unlocked_bootstrap	chip_sw_exit_test_unlocked_bootstrap	2.340m		0	1	0.00
V2	chip_sw_inject_scramble_seed	chip_sw_inject_scramble_seed	2.003m		0	1	0.00
V2	tl_d_oob_addr_access	chip_tl_errors	2.673m	4.960ms	0	1	0.00
V2	tl_d_illegal_access	chip_tl_errors	2.673m	4.960ms	0	1	0.00
V2	tl_d_outstanding_access	chip_csr_aliasing	9.640s		0	1	0.00
		chip_same_csr_outstanding	9.830s		0	1	0.00
V2	tl_d_partial_access	chip_csr_aliasing	9.640s		0	1	0.00
		chip_same_csr_outstanding	9.830s		0	1	0.00
V2	xbar_base_random_sequence	xbar_random	25.270s	23.086us	1	1	100.00
V2	xbar_random_delay	xbar_smoke_zero_delays	8.560s	11.904us	1	1	100.00
		xbar_smoke_large_delays	4.723m	2.576ms	1	1	100.00
		xbar_smoke_slow_rsp	5.197m	2.035ms	1	1	100.00
		xbar_random_zero_delays	1.308m	71.680us	1	1	100.00
		xbar_random_large_delays	20.400m	10.943ms	1	1	100.00
		xbar_random_slow_rsp	22.904m	8.991ms	1	1	100.00
V2	xbar_unmapped_address	xbar_unmapped_addr	26.000s	17.826us	1	1	100.00
		xbar_error_and_unmapped_addr	29.930s	26.274us	1	1	100.00
V2	xbar_error_cases	xbar_error_random	1.782m	286.449us	1	1	100.00
		xbar_error_and_unmapped_addr	29.930s	26.274us	1	1	100.00
V2	xbar_all_access_same_device	xbar_access_same_device	40.130s	101.708us	1	1	100.00
		xbar_access_same_device_slow_rsp	36.754m	14.455ms	1	1	100.00
V2	xbar_all_hosts_use_same_source_id	xbar_same_source	1.757m	336.285us	1	1	100.00
V2	xbar_stress_all	xbar_stress_all	1.037m	43.190us	1	1	100.00
		xbar_stress_all_with_error	14.660m	2.877ms	1	1	100.00
V2	xbar_stress_with_reset	xbar_stress_all_with_rand_reset	43.520s	9.076us	1	1	100.00
		xbar_stress_all_with_reset_error	3.458m	212.808us	1	1	100.00
V2	rom_e2e_smoke	rom_e2e_smoke	11.040s		0	1	0.00
V2	rom_e2e_shutdown_output	rom_e2e_shutdown_output	11.032s		0	1	0.00
V2	rom_e2e_shutdown_exception_c	rom_e2e_shutdown_exception_c	11.035s		0	1	0.00
V2	rom_e2e_boot_policy_valid	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	11.056s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_dev	14.086s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod	14.096s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod_end	11.061s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_rma	11.061s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	12.082s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_dev	13.091s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod	12.089s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	12.086s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_rma	11.080s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	12.083s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_dev	13.087s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod	13.092s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	12.077s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_rma	12.091s		0	1	0.00
V2	rom_e2e_sigverify_always	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	13.107s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_dev	12.101s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod	12.106s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod_end	12.105s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_rma	13.109s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	13.109s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_dev	13.110s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod	12.103s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	12.106s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_rma	12.099s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	12.096s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_dev	13.098s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod	12.093s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	13.100s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_rma	12.093s		0	1	0.00
V2	rom_e2e_asm_init	rom_e2e_asm_init_test_unlocked0	12.097s		0	1	0.00
		rom_e2e_asm_init_dev	12.096s		0	1	0.00
		rom_e2e_asm_init_prod	12.095s		0	1	0.00
		rom_e2e_asm_init_prod_end	13.101s		0	1	0.00
		rom_e2e_asm_init_rma	12.088s		0	1	0.00
V2	rom_e2e_keymgr_init	rom_e2e_keymgr_init_rom_ext_meas	12.123s		0	1	0.00
		rom_e2e_keymgr_init_rom_ext_no_meas	11.117s		0	1	0.00
		rom_e2e_keymgr_init_rom_ext_invalid_meas	12.123s		0	1	0.00
V2	rom_e2e_static_critical	rom_e2e_static_critical	12.112s		0	1	0.00
V2		TOTAL			65	206	31.55
V2S	chip_sw_aes_masking_off	chip_sw_aes_masking_off	4.951m	5.883ms	1	1	100.00
V2S	chip_sw_rv_core_ibex_lockstep_glitch	chip_sw_rv_core_ibex_lockstep_glitch	3.868m	5.507ms	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	chip_rv_dm_perform_debug	rom_e2e_jtag_debug_test_unlocked0	13.109s		0	1	0.00
		rom_e2e_jtag_debug_dev	12.102s		0	1	0.00
		rom_e2e_jtag_debug_rma	11.078s		0	1	0.00
V3	chip_sw_rv_dm_access_after_hw_reset	chip_sw_rv_dm_access_after_escalation_reset	12.058s		0	1	0.00
V3	chip_sw_plic_alerts	chip_sw_all_escalation_resets	15.027m	17.570ms	0	1	0.00
V3	chip_sw_otp_ctrl_vendor_test_csr_access	chip_sw_otp_ctrl_vendor_test_csr_access	18.146s		0	1	0.00
V3	chip_sw_otp_ctrl_escalation	chip_sw_otp_ctrl_escalation	13.033m	15.951ms	0	1	0.00
V3	chip_sw_coremark	chip_sw_coremark	11.027s		0	1	0.00
V3	chip_sw_power_max_load	chip_sw_power_virus	12.029s		0	1	0.00
V3	rom_e2e_debug	rom_e2e_jtag_debug_test_unlocked0	13.109s		0	1	0.00
		rom_e2e_jtag_debug_dev	12.102s		0	1	0.00
		rom_e2e_jtag_debug_rma	11.078s		0	1	0.00
V3	rom_e2e_jtag_inject	rom_e2e_jtag_inject_test_unlocked0	12.110s		0	1	0.00
		rom_e2e_jtag_inject_dev	11.101s		0	1	0.00
		rom_e2e_jtag_inject_rma	12.115s		0	1	0.00
V3	rom_e2e_self_hash	rom_e2e_self_hash	52.217s		0	1	0.00
V3		TOTAL			0	12	0.00
	Unmapped tests	chip_sw_rstmgr_rst_cnsty_escalation	16.362m	12.576ms	1	1	100.00
		chip_sw_dma_inline_hashing	4.306m	4.009ms	1	1	100.00
		chip_sw_dma_abort	3.796m	3.446ms	0	1	0.00
		rom_e2e_sigverify_mod_exp_test_unlocked0_otbn	12.124s		0	1	0.00
		rom_e2e_sigverify_mod_exp_test_unlocked0_sw	12.130s		0	1	0.00
		rom_e2e_sigverify_mod_exp_dev_otbn	11.111s		0	1	0.00
		rom_e2e_sigverify_mod_exp_dev_sw	12.124s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_otbn	12.121s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_sw	12.118s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_end_otbn	11.128s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_end_sw	11.124s		0	1	0.00
		rom_e2e_sigverify_mod_exp_rma_otbn	11.120s		0	1	0.00
		rom_e2e_sigverify_mod_exp_rma_sw	12.131s		0	1	0.00
		chip_sw_mbx_smoketest	3.936m	4.188ms	1	1	100.00
		TOTAL			73	246	29.67

Failure Buckets

Job returned non-zero exit code has 145 failures:

Test chip_sw_example_rom has 1 failures.

0.chip_sw_example_rom.93966843940992670385056791194913067403749470738091342531940002970734478489977
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_example_rom/latest/run.log

  Target //sw/device/tests:example_test_from_rom_sim_dv failed to build
  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests:example_test_from_rom_sim_dv' failed; build aborted: Target //sw/device/tests:example_test_from_rom_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests:example_test_from_rom_sim_dv (be0d27)
      //hw/top_earlgrey/sw/autogen:top_earlgrey (87ed6c)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 59.335s, Critical Path: 0.05s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_example_manufacturer has 1 failures.

0.chip_sw_example_manufacturer.98639634641905145642904304039294891893227389516137188811685601978095124040388
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_example_manufacturer/latest/run.log

  Analyzing: target @@+hooks+manufacturer_test_hooks//:example_test_sim_dv (1 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '@@+hooks+manufacturer_test_hooks//:example_test_sim_dv' failed; build aborted: Target @@+hooks+manufacturer_test_hooks//:example_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      @@+hooks+manufacturer_test_hooks//:example_test_sim_dv (889ebe)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 59.393s, Critical Path: 0.02s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_data_integrity_escalation has 1 failures.

0.chip_sw_data_integrity_escalation.82062957371376650655287602480950423318012537137904329567081040762232127580028
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_data_integrity_escalation/latest/run.log

  Analyzing: target //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv (7f044c)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 130.735s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_sleep_pin_wake has 1 failures.

0.chip_sw_sleep_pin_wake.97383885244285626977982977749844616494255651184728863691337536148068887242642
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_sleep_pin_wake/latest/run.log

  Analyzing: target //sw/device/tests:sleep_pin_wake_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests:sleep_pin_wake_test_sim_dv' failed; build aborted: Target //sw/device/tests:sleep_pin_wake_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests:sleep_pin_wake_test_sim_dv (719def)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 125.747s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_sleep_pin_retention has 1 failures.

0.chip_sw_sleep_pin_retention.52954520947639977515018513201272416705029971333241850002405713690348880741549
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_sleep_pin_retention/latest/run.log

  Analyzing: target //sw/device/tests:sleep_pin_retention_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests:sleep_pin_retention_test_sim_dv' failed; build aborted: Target //sw/device/tests:sleep_pin_retention_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests:sleep_pin_retention_test_sim_dv (f809ef)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 125.183s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

... and 140 more tests.

UVM_FATAL @ * us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat" has 9 failures:
- Test chip_sw_aes_enc_jitter_en has 1 failures.
  - 0.chip_sw_aes_enc_jitter_en.24802422373578914060119972761891248996756864396726235334672307190271362045720
    Line 432, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aes_enc_jitter_en/latest/run.log
```
  UVM_FATAL @  10.160001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_hmac_enc_jitter_en has 1 failures.
  - 0.chip_sw_hmac_enc_jitter_en.39632720582562144467854344617895774646371483689366474083329035545174828559064
    Line 411, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_hmac_enc_jitter_en/latest/run.log
```
  UVM_FATAL @  10.180001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.180001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_keymgr_dpe_key_derivation_jitter_en has 1 failures.
  - 0.chip_sw_keymgr_dpe_key_derivation_jitter_en.65722107632162447925490192225048495015030945226131742825455585515776423212146
    Line 416, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation_jitter_en/latest/run.log
```
  UVM_FATAL @  10.240001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_kmac_mode_kmac_jitter_en has 1 failures.
  - 0.chip_sw_kmac_mode_kmac_jitter_en.108556976064607868500851736486551436868978959659573201380832247710034159287431
    Line 416, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_kmac_mode_kmac_jitter_en/latest/run.log
```
  UVM_FATAL @  10.280001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_aes_enc_jitter_en_reduced_freq has 1 failures.
  - 0.chip_sw_aes_enc_jitter_en_reduced_freq.14409231416288011480179700544269927580742530978437897630744241983739066256020
    Line 424, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aes_enc_jitter_en_reduced_freq/latest/run.log
```
  UVM_FATAL @  10.320001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- ... and 4 more tests.
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode has 3 failures:
- Test chip_csr_bit_bash has 1 failures.
  - 0.chip_csr_bit_bash.3568056360632862704542385338095663039254160210426516118348251593938353327500
    Line 131, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_csr_bit_bash/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_csr_aliasing has 1 failures.
  - 0.chip_csr_aliasing.35781985807443488482378879346489049763873713171569195138061355078272807495868
    Line 131, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_csr_aliasing/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_same_csr_outstanding has 1 failures.
  - 0.chip_same_csr_outstanding.65576552933710140550440541649327208540084570449493863055102305781954094054605
    Line 131, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_same_csr_outstanding/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (chip_sw_base_vseq.sv:434) virtual_sequencer [chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns has 3 failures:

Test chip_sw_rstmgr_alert_info has 1 failures.

0.chip_sw_rstmgr_alert_info.35433940789922557536287996821366015383853137207040449572310673588566729242427
Line 467, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rstmgr_alert_info/latest/run.log

  UVM_ERROR @ 30015.821342 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 30000000 ns

  UVM_INFO @ 30015.821342 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_rstmgr_cpu_info has 1 failures.

0.chip_sw_rstmgr_cpu_info.25585884257380010592729351492576016818000106568904994360181497964455928307614
Line 473, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rstmgr_cpu_info/latest/run.log

  UVM_ERROR @ 20025.023431 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 20000000 ns

  UVM_INFO @ 20025.023431 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_aon_timer_irq has 1 failures.

0.chip_sw_aon_timer_irq.111807892095478248825141578767447001291390428373523596955945033916900280005620
Line 522, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aon_timer_irq/latest/run.log

  UVM_ERROR @ 18015.532793 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 18000000 ns

  UVM_INFO @ 18015.532793 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:529) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@46337) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 2 failures:

Test chip_jtag_csr_rw has 1 failures.

0.chip_jtag_csr_rw.88608875923366208921545904123338316392031336501355697206341879290830171051200
Line 6143, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_jtag_csr_rw/latest/run.log

  UVM_ERROR @ 3407.354409 us: (cip_base_scoreboard.sv:529) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@46337) { a_addr: 'h30480000  a_data: 'hcec932bc  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h30  a_opcode: 'h0  a_user: 'h2690a  d_param: 'h0  d_source: 'h30  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 1, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 3407.354409 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_jtag_mem_access has 1 failures.

0.chip_jtag_mem_access.13831024065333621386840722672381858989581061224326499275826951976058156181704
Line 6143, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_jtag_mem_access/latest/run.log

  UVM_ERROR @ 3881.362743 us: (cip_base_scoreboard.sv:529) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@46337) { a_addr: 'h30480000  a_data: 'h8843731f  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'hf  a_opcode: 'h0  a_user: 'h2690a  d_param: 'h0  d_source: 'hf  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 1, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 3881.362743 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (chip_sw_base_vseq.sv:434) virtual_sequencer [chip_sw_all_escalation_resets_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns has 1 failures:
- Test chip_sw_all_escalation_resets has 1 failures.
  - 0.chip_sw_all_escalation_resets.84119667056733471423365071322134073063953762772655872520495770262383348657570
    Line 534, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_all_escalation_resets/latest/run.log
```
  UVM_ERROR @ 17570.263288 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_all_escalation_resets_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 12000000 ns

  UVM_INFO @ 17570.263288 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty has 1 failures:
- Test chip_sw_spi_device_pass_through_collision has 1 failures.
  - 0.chip_sw_spi_device_pass_through_collision.94078892167140027942996496695522101335623614845395719251408520946186211862897
    Line 690, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_spi_device_pass_through_collision/latest/run.log
```
  UVM_ERROR @ 4322.981006 us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty
  UVM_INFO @ 4322.981006 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_base_vseq.sv:434) virtual_sequencer [chip_sw_otp_ctrl_escalation_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns has 1 failures:
- Test chip_sw_otp_ctrl_escalation has 1 failures.
  - 0.chip_sw_otp_ctrl_escalation.49068242626926175394437691243861809095526469991507989432417856570182910687609
    Line 483, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_otp_ctrl_escalation/latest/run.log
```
  UVM_ERROR @ 15950.919476 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_otp_ctrl_escalation_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 12000000 ns

  UVM_INFO @ 15950.919476 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_soc_proxy_external_alerts_vseq.sv:74) [chip_sw_soc_proxy_external_alerts_vseq] Check failed alert_rsp == alert_req (* [*] vs * [*]) Alert response incorrect! has 1 failures:
- Test chip_sw_soc_proxy_external_alerts has 1 failures.
  - 0.chip_sw_soc_proxy_external_alerts.77049927758049270180536901557029947477249509569805897278440812793292232024385
    Line 496, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_soc_proxy_external_alerts/latest/run.log
```
  UVM_ERROR @ 5508.550968 us: (chip_sw_soc_proxy_external_alerts_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.chip_sw_soc_proxy_external_alerts_vseq] Check failed alert_rsp == alert_req (93824992236885 [0x555555555555] vs 93824992236886 [0x555555555556]) Alert response incorrect!
  UVM_INFO @ 5508.550968 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [rv_core_ibex_nmi_irq_test_sim_dv(sw/device/tests/rv_core_ibex_nmi_irq_test.c:172)] CHECK-fail: Timed out after * usec (* CPU cycles) waiting for nmi_fired has 1 failures:
- Test chip_sw_rv_core_ibex_nmi_irq has 1 failures.
  - 0.chip_sw_rv_core_ibex_nmi_irq.41922934052350219454284371889760065338101721272463911893227122235627970932737
    Line 457, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rv_core_ibex_nmi_irq/latest/run.log
```
  UVM_ERROR @ 6013.654680 us: (sw_logger_if.sv:526) [rv_core_ibex_nmi_irq_test_sim_dv(sw/device/tests/rv_core_ibex_nmi_irq_test.c:172)] CHECK-fail: Timed out after 1000 usec (100000 CPU cycles) waiting for nmi_fired
  UVM_INFO @ 6013.654680 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:74) [chip_sw_keymgr_dpe_key_derivation_vseq] Timed out waiting for keymgr_dpe to derive boot stage * key has 1 failures:
- Test chip_sw_keymgr_dpe_key_derivation has 1 failures.
  - 0.chip_sw_keymgr_dpe_key_derivation.69065819285644724305398502704352608688496516196166990609284551790146048611271
    Line 415, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation/latest/run.log
```
  UVM_FATAL @ 20010.300001 us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_dpe_key_derivation_vseq] Timed out waiting for keymgr_dpe to derive boot stage 0 key
  UVM_INFO @ 20010.300001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:489) [chip_sw_keymgr_dpe_key_derivation_vseq] Check failed keymgr_pkg::KeyWidth'(get_kmac_digest(kmac_key, data_arr)) == act_digest (* [*] vs * [*]) has 1 failures:

Test chip_sw_keymgr_dpe_key_derivation_prod has 1 failures.

0.chip_sw_keymgr_dpe_key_derivation_prod.57518998460436184192878106394979080805617800623579256634233142827476992243037
Line 460, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation_prod/latest/run.log

  UVM_ERROR @ 7556.243930 us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:489) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_dpe_key_derivation_vseq] Check failed keymgr_pkg::KeyWidth'(get_kmac_digest(kmac_key, data_arr)) == act_digest (93368079065459786547999136278471176993142674383713154695330849635331953919173 [0xce6c75c37987d82bf19485d7087e1ca4292059b0c7c94f908a38be59230404c5] vs 46626776232224564586206825405402486595992965517070340592229234387262020557013 [0x6715d1f3df789eae0696c3dc312374b7d84cfef4afcace6ff3e562c7271098d5])
  UVM_INFO @ 7556.243930 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[RamCtn0]] file kmac_app_rom_test_sim_dv.*.vmem could not be opened for r mode has 1 failures:
- Test chip_sw_kmac_app_rom has 1 failures.
  - 0.chip_sw_kmac_app_rom.946284207187165551900290183572977011974501356604932358179289220146813968279
    Line 432, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_kmac_app_rom/latest/run.log
```
  UVM_FATAL @  10.280001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[RamCtn0]] file kmac_app_rom_test_sim_dv.32.vmem could not be opened for r mode
  UVM_INFO @  10.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Offending '(tl_h_i[*].a_source[(IDW - *)-:STIDW] == '0)' has 1 failures:
- Test chip_tl_errors has 1 failures.
  - 0.chip_tl_errors.10463816003302746869825597082577351477242038284792016688166468459669400057903
    Line 255, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_tl_errors/latest/run.log
```
      Offending '(tl_h_i[0].a_source[(IDW - 1)-:STIDW] == '0)'
  UVM_ERROR @ 4960.246760 us: (tlul_socket_m1.sv:101) [ASSERT FAILED] idInRange
  UVM_INFO @ 4960.246760 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Error-[CNST-CIF] Constraints inconsistency failure has 1 failures:
- Test chip_padctrl_attributes has 1 failures.
  - 0.chip_padctrl_attributes.57250419011288402273057425788751222569536231347081566013845765142341766168778
    Line 301, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_padctrl_attributes/latest/run.log
```
  Error-[CNST-CIF] Constraints inconsistency failure
  ../src/lowrisc_dv_dv_lib_0/dv_base_test.sv, 95
    Constraints are inconsistent and cannot be solved.
    Please check the inconsistent constraints being printed above and rewrite
    them.
```
UVM_FATAL @ * us: sequencer [sequencer] Item_done() called with no outstanding requests. Each call to item_done() must be paired with a previous call to get_next_item(). has 1 failures:
- Test chip_sw_dma_abort has 1 failures.
  - 0.chip_sw_dma_abort.12714473516059445610010746673692111705875539691334061886317874715746062036482
    Line 427, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_dma_abort/latest/run.log
```
  UVM_FATAL @ 3446.245208 us: uvm_test_top.env.m_spi_device_agents0.sequencer [uvm_test_top.env.m_spi_device_agents0.sequencer] Item_done() called with no outstanding requests. Each call to item_done() must be paired with a previous call to get_next_item().
  UVM_INFO @ 3446.245208 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```