CSRNG Simulation Results

Tuesday April 08 2025 17:07:09 UTC

GitHub Revision: 6f17fda

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	csrng_smoke	5.000s	89.945us	1	1	100.00
V1	csr_hw_reset	csrng_csr_hw_reset	5.000s	42.937us	1	1	100.00
V1	csr_rw	csrng_csr_rw	4.000s	13.686us	1	1	100.00
V1	csr_bit_bash	csrng_csr_bit_bash	10.000s	189.137us	1	1	100.00
V1	csr_aliasing	csrng_csr_aliasing	6.000s	58.487us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	csrng_csr_mem_rw_with_rand_reset	4.000s	24.823us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	csrng_csr_rw	4.000s	13.686us	1	1	100.00
		csrng_csr_aliasing	6.000s	58.487us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	interrupts	csrng_intr	7.000s	69.018us	1	1	100.00
V2	alerts	csrng_alert	9.000s	91.626us	1	1	100.00
V2	err	csrng_err	5.000s	20.156us	1	1	100.00
V2	cmds	csrng_cmds	1.267m	2.995ms	1	1	100.00
V2	life cycle	csrng_cmds	1.267m	2.995ms	1	1	100.00
V2	stress_all	csrng_stress_all	2.233m	6.490ms	0	1	0.00
V2	intr_test	csrng_intr_test	5.000s	59.629us	1	1	100.00
V2	alert_test	csrng_alert_test	5.000s	35.859us	1	1	100.00
V2	tl_d_oob_addr_access	csrng_tl_errors	9.000s	111.473us	1	1	100.00
V2	tl_d_illegal_access	csrng_tl_errors	9.000s	111.473us	1	1	100.00
V2	tl_d_outstanding_access	csrng_csr_hw_reset	5.000s	42.937us	1	1	100.00
		csrng_csr_rw	4.000s	13.686us	1	1	100.00
		csrng_csr_aliasing	6.000s	58.487us	1	1	100.00
		csrng_same_csr_outstanding	5.000s	52.684us	1	1	100.00
V2	tl_d_partial_access	csrng_csr_hw_reset	5.000s	42.937us	1	1	100.00
		csrng_csr_rw	4.000s	13.686us	1	1	100.00
		csrng_csr_aliasing	6.000s	58.487us	1	1	100.00
		csrng_same_csr_outstanding	5.000s	52.684us	1	1	100.00
V2		TOTAL			8	9	88.89
V2S	tl_intg_err	csrng_sec_cm	7.000s	101.173us	1	1	100.00
		csrng_tl_intg_err	11.000s	438.666us	1	1	100.00
V2S	sec_cm_config_regwen	csrng_regwen	4.000s	11.795us	1	1	100.00
		csrng_csr_rw	4.000s	13.686us	1	1	100.00
V2S	sec_cm_config_mubi	csrng_alert	9.000s	91.626us	1	1	100.00
V2S	sec_cm_intersig_mubi	csrng_stress_all	2.233m	6.490ms	0	1	0.00
V2S	sec_cm_main_sm_fsm_sparse	csrng_intr	7.000s	69.018us	1	1	100.00
		csrng_err	5.000s	20.156us	1	1	100.00
		csrng_sec_cm	7.000s	101.173us	1	1	100.00
V2S	sec_cm_update_fsm_sparse	csrng_intr	7.000s	69.018us	1	1	100.00
		csrng_err	5.000s	20.156us	1	1	100.00
		csrng_sec_cm	7.000s	101.173us	1	1	100.00
V2S	sec_cm_blk_enc_fsm_sparse	csrng_intr	7.000s	69.018us	1	1	100.00
		csrng_err	5.000s	20.156us	1	1	100.00
		csrng_sec_cm	7.000s	101.173us	1	1	100.00
V2S	sec_cm_outblk_fsm_sparse	csrng_intr	7.000s	69.018us	1	1	100.00
		csrng_err	5.000s	20.156us	1	1	100.00
		csrng_sec_cm	7.000s	101.173us	1	1	100.00
V2S	sec_cm_gen_cmd_ctr_redun	csrng_intr	7.000s	69.018us	1	1	100.00
		csrng_err	5.000s	20.156us	1	1	100.00
		csrng_sec_cm	7.000s	101.173us	1	1	100.00
V2S	sec_cm_drbg_upd_ctr_redun	csrng_intr	7.000s	69.018us	1	1	100.00
		csrng_err	5.000s	20.156us	1	1	100.00
		csrng_sec_cm	7.000s	101.173us	1	1	100.00
V2S	sec_cm_drbg_gen_ctr_redun	csrng_intr	7.000s	69.018us	1	1	100.00
		csrng_err	5.000s	20.156us	1	1	100.00
		csrng_sec_cm	7.000s	101.173us	1	1	100.00
V2S	sec_cm_ctrl_mubi	csrng_alert	9.000s	91.626us	1	1	100.00
V2S	sec_cm_main_sm_ctr_local_esc	csrng_intr	7.000s	69.018us	1	1	100.00
		csrng_err	5.000s	20.156us	1	1	100.00
V2S	sec_cm_constants_lc_gated	csrng_stress_all	2.233m	6.490ms	0	1	0.00
V2S	sec_cm_sw_genbits_bus_consistency	csrng_alert	9.000s	91.626us	1	1	100.00
V2S	sec_cm_tile_link_bus_integrity	csrng_tl_intg_err	11.000s	438.666us	1	1	100.00
V2S	sec_cm_aes_cipher_fsm_sparse	csrng_intr	7.000s	69.018us	1	1	100.00
		csrng_err	5.000s	20.156us	1	1	100.00
		csrng_sec_cm	7.000s	101.173us	1	1	100.00
V2S	sec_cm_aes_cipher_fsm_redun	csrng_intr	7.000s	69.018us	1	1	100.00
		csrng_err	5.000s	20.156us	1	1	100.00
V2S	sec_cm_aes_cipher_ctrl_sparse	csrng_intr	7.000s	69.018us	1	1	100.00
		csrng_err	5.000s	20.156us	1	1	100.00
V2S	sec_cm_aes_cipher_fsm_local_esc	csrng_intr	7.000s	69.018us	1	1	100.00
		csrng_err	5.000s	20.156us	1	1	100.00
V2S	sec_cm_aes_cipher_ctr_redun	csrng_intr	7.000s	69.018us	1	1	100.00
		csrng_err	5.000s	20.156us	1	1	100.00
		csrng_sec_cm	7.000s	101.173us	1	1	100.00
V2S	sec_cm_aes_cipher_data_reg_local_esc	csrng_intr	7.000s	69.018us	1	1	100.00
		csrng_err	5.000s	20.156us	1	1	100.00
V2S		TOTAL			3	3	100.00
V3	stress_all_with_rand_reset	csrng_stress_all_with_rand_reset	25.000s	951.229us	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			17	19	89.47

Failure Buckets

• UVM_ERROR (csrng_scoreboard.sv:166) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [*] vs * [*]) Interrupt_pin: EntropyReq has 1 failures:

  • Test csrng_stress_all has 1 failures.

    • 0.csrng_stress_all.44191323249070197011432916893286804910039921086254840218369458429742407356669
      Line 144, in log /nightly/runs/scratch/master/csrng-sim-xcelium/0.csrng_stress_all/latest/run.log

        UVM_ERROR @ 6490135272 ps: (csrng_scoreboard.sv:166) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
        UVM_INFO @ 6490135272 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:908) [csrng_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:

  • Test csrng_stress_all_with_rand_reset has 1 failures.

    • 0.csrng_stress_all_with_rand_reset.64561576132102034665216189787900830029809090250235428957924605465811792933315
      Line 123, in log /nightly/runs/scratch/master/csrng-sim-xcelium/0.csrng_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 951229185 ps: (cip_base_vseq.sv:908) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 951229185 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---